# US 12,222,829 B2 · Memory module with dedicated repair devices

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- Number: US 12,222,829 B2
- Document ID: US12222829B2
- Status: Granted
- Kind: B2
- Application number: 18/373,219
- Filed: 2023-09-26
- Published: 2024-03-21
- Granted: 2025-02-11
- Earliest claimed: 2014-02-28
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; Brent S. Haukness; John Eric Linstadt; Scott C. Best
- Web page: https://patentgrep.com/patent/US12222829B2

## CPC

- G06F 11/2094: {Redundant storage or storage space (G06F11/2056 takes precedence)}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/76: {using address translation or modifications}
- G11C 29/81: {using a hierarchical redundancy scheme}
- G11C 29/846: {by choosing redundant lines at an output stage}
- G06F 2201/82: Solving problems relating to consistency
- G11C 2029/0403: {during or with feedback to manufacture}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

## Claims

### Claim 1

A memory device, comprising:
an array of storage locations dedicated to store failure address information associated with defective storage locations in a second memory device, the failure address information accessible during a first access operation that at least partially overlaps a second access operation directed to the defective storage locations of the second memory device; and
interface circuitry coupled to a memory repair circuit to receive a command for executing the first access operation.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein:
the second access operation comprises a read operation or a write operation carried out during a first access time interval; and
wherein the first access operation comprises a read operation or a write operation carried out during a second access time interval that temporally overlaps at least a portion of the first access time interval.

### Claim 3 (depends on 1)

The memory device according to claim 1, wherein:
the command for executing the first access operation comprises a read command; and
wherein the interface circuitry transmits at least a portion of the failure address information as read data to the memory repair circuit in response to the read command.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein:
the command for executing the first access operation comprises a write command; and
wherein the interface circuitry receives updated failure address information as write data from the memory repair circuit in response to the write command.

### Claim 5 (depends on 1)

The memory device according to claim 1, realized as a dynamic random access memory (DRAM) device.

### Claim 6 (depends on 1)

The memory device according to claim 1, wherein the failure address information is encoded via an error code.

### Claim 7 (depends on 6)

The memory device according to claim 6, wherein the error code comprises an error detection code (EDC).

### Claim 8

A method of operation in a memory device, the method comprising:
receiving a command for executing a first access operation; and
accessing, in response to the command, storage locations dedicated to store failure address information associated with defective storage locations in a second memory device, the accessing at least partially overlapping a second access operation directed to the defective storage locations of the second memory device.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
the second access operation comprises a read operation or a write operation carried out during a first access time interval; and
wherein the accessing comprises performing a read operation or a write operation during a second access time interval that temporally overlaps at least a portion of the first access time interval.

### Claim 10 (depends on 8)

The method of claim 8, wherein:
the command for executing the first access operation comprises a read command; and
wherein the accessing further comprises transmitting at least a portion of the failure address information as read data to a memory repair circuit in response to the read command.

### Claim 11 (depends on 8)

The method of claim 8 wherein:
the command for executing the first access operation comprises a write command; and
wherein the accessing further comprises receiving updated failure address information as write data from a memory repair circuit in response to the write command.

### Claim 12 (depends on 8)

The method of claim 8, wherein:
the command for executing the first access operation is compliant with a dynamic random access memory (DRAM) protocol.

### Claim 13 (depends on 8)

The method of claim 8, wherein:
applying an error code to the data and the failure address information stored in the memory device and the second memory device.

### Claim 14 (depends on 8)

The memory device according to claim 8, wherein the failure address information is encoded via an error code.

### Claim 15 (depends on 14)

The memory device according to claim 14, wherein the error code comprises an error detection code (EDC).

### Claim 16

An integrated circuit (IC) dynamic random access memory (DRAM) chip, comprising:
an array of storage locations dedicated to store failure address information associated with defective storage locations in a second IC DRAM chip, the failure address information accessible during a first access operation that at least partially overlaps a second access operation directed to the defective storage locations of the second IC DRAM chip; and
interface circuitry coupled to a memory repair circuit to receive a command for executing the first access operation.

### Claim 17 (depends on 16)

The IC DRAM chip of claim 16, wherein:
the second access operation comprises a read operation or a write operation carried out during a first access time interval; and
wherein the first access operation comprises a read operation or a write operation carried out during a second access time interval that temporally overlaps at least a portion of the first access time interval.

### Claim 18 (depends on 16)

The IC DRAM chip of claim 16, wherein:
the command for executing the first access operation comprises a read command; and
wherein the interface circuitry transmits at least a portion of the failure address information as read data to the memory repair circuit in response to the read command.

### Claim 19 (depends on 16)

The IC DRAM chip of claim 16, wherein:
the command for executing the first access operation comprises a write command; and
wherein the interface circuitry receives updated failure address information as write data from the memory repair circuit in response to the write command.

### Claim 20 (depends on 16)

The IC DRAM chip of claim 16, wherein the failure address information is encoded via an error code.