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US 12,222,806 B2Granted
Cache line data protection
AssigneeMicron Technology, Inc.
InventorsMarco Sforzin, Paolo Amato
Life of this patent
Estimating the term…
Abstract
Data protection with error correction/detection capabilities can be provided on a cache line basis. When provided on a cache line basis to collectively protect the cache line data, the error correction/detection capabilities can be provided with fewer number of bits (e.g., error correction code (ECC) and/or cyclic redundancy check (CRC) bits) as compared to providing the same error correction/detection capabilities individually on a subset of the cache line data.
Claims20
An apparatus, comprising:
- a number of memory devices;
- and
- a memory controller coupled to the number of memory devices, the memory controller configured to:
- receive a plurality of user data blocks (UDBs) corresponding to a cache line and belonging to different stripes, wherein the plurality of UDBs corresponding to the cache line is a data transfer unit to or from a cache;
- generate error detection information based collectively on the plurality of UDBs corresponding to the cache line;
- generate error correction information based collectively on the plurality of UDBs corresponding to the cache line;
- and
- write, along with the error detection information and error correction information, the plurality of UDBs to the number of memory devices;
- read the plurality of UDBs;
- and
- in response to the plurality of UDBs being indicated as containing one or more errors:
- perform one second error correction operation on a first subset of the plurality of UDBs using a first parity data block;
- and
- perform, independently of the one second error correction operation, another second error correction operation on a second subset of the plurality of UDBs using a second parity data block.
11 more elements
An apparatus, comprising:
- a number of memory devices;
- and
- a memory controller coupled to the number of memory devices, the memory controller configured to:
- receive, from the number of memory devices, a plurality of user data blocks (UDBs) corresponding to a cache line, wherein the plurality of UDBs belong to respective different stripes;
- perform, to correct a quantity of bit errors within the plurality of UDBs, a first error correction operation collectively on the plurality of UDBs using error correction information generated based collectively on the plurality of UDBs;
- and
- perform, to determine whether to perform one or more second error correction operations on the plurality of UDBs, a first error detection operation collectively on the plurality of UDBs using error detection information generated based collectively on the plurality of UDBs;
- and
- responsive to the first error detection operation indicating that the plurality of UDBs still contains one or more errors:
- perform one second error correction operation on a first subset of the plurality of UDBs using a first parity data block;
- and
- perform, independently of the one second error correction operation, another second error correction operation on a second subset of the plurality of UDBs using a second parity data block.
9 more elements
A method, comprising:
- transferring, from a number of memory devices, a plurality of user data blocks (UDBs) corresponding to a cache line, wherein the plurality of UDBs belong to respective different stripes;
- performing, using first error correction information generated based collectively on the plurality of UDBs, a first error correction operation on the plurality of UDBs to correct a quantity of errors or detect errors more than the quantity of errors;
- performing, subsequent to the first error correction operation and using first error detection information generated based collectively on the plurality of UDBs, a first error detection operation on the plurality of UDBs to determine if the plurality of UDBs still contains one or more bit errors;
- and
- responsive to the first error detection operation indicating that the plurality of UDBs still contains the one or more errors;
- performing one second error correction operation on a first subset of the plurality of UDBs using a first parity data block;
- and
- performing, independently of the one second error correction operation, another second error correction operation on a second subset of the plurality of UDBs using a second parity data block.
5 more elements
Dependencies are inferred from the claim text.