# US 12,222,797 B2 · Dynamic configuration of processor sub-components

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- Number: US 12,222,797 B2
- Document ID: US12222797B2
- Status: Granted
- Kind: B2
- Application number: 18/084,499
- Filed: 2022-12-19
- Published: 2024-06-20
- Granted: 2025-02-11
- Earliest claimed: 2022-12-19
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: James Mossman; Robert Cohen; Sudherssen Kalaiselvan; Tzu-Wei Lin
- Web page: https://patentgrep.com/patent/US12222797B2

## CPC

- G06F 1/3296: by lowering the supply or operating voltage
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 1/3287: by switching off individual functional units in the computer system
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

## Claims

### Claim 1

A method comprising:
observing, using a control circuit coupled to a target sub-component of a functional unit of a processor, a utilization of the target sub-component, wherein the target sub-component corresponds to one of a plurality of pipelines executing in parallel;
detecting that the utilization is outside a desired utilization range; and
throttling at least one sub-component of the functional unit to shut off the one of the plurality of pipelines.

### Claim 2 (depends on 1)

The method of claim 1, further comprising observing, using the control circuit, a workload that is input into the target sub-component.

### Claim 3 (depends on 2)

The method of claim 2, wherein the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component.

### Claim 4 (depends on 2)

The method of claim 2, wherein the at least one sub-component of the functional unit is selected for throttling based on a workload type of the workload.

### Claim 5 (depends on 2)

The method of claim 2, wherein the workload corresponds to a minimal workload and the at least one sub-component corresponds to the target sub-component.

### Claim 6 (depends on 1)

The method of claim 1, wherein throttling the at least one sub-component comprises putting the at least one sub-component into a low-power state.

### Claim 7 (depends on 1)

The method of claim 1, wherein throttling the at least one sub-component comprises throttling the functional unit.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
detecting that the utilization is within the desired utilization range; and
dethrottling the at least one sub-component in response to detecting that the utilization is within the desired utilization range.

### Claim 9 (depends on 1)

The method of claim 1, wherein:
the target sub-component corresponds to a micro-operation cache for storing predecoded instructions;
the functional unit further comprises at least a first pipeline and a second pipeline each comprising sub-components for providing predecoded instructions to the micro-operation cache; and
the at least one sub-component corresponds to at least one of the first and second pipelines.

### Claim 10 (depends on 1)

The method of claim 1, wherein the functional unit corresponds to at least one of an arithmetic logic unit (ALU), a floating-point unit (FPU), or a load-store unit (LSU).

### Claim 11 (depends on 1)

The method of claim 1, wherein the processor corresponds to a multi-core processor and the functional unit corresponds to a core of the multi-core processor.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
detecting, using a higher-level control circuit coupled to the control circuit, the throttling of the at least one sub-component of the functional unit, wherein the higher-level control circuit is further coupled to a second control circuit that is coupled to a second target sub-component of a second functional unit of the processor; and
coordinating, using the higher-level control circuit, throttling of sub-components by the control circuit and the second control circuit.

### Claim 13

A method comprising:
observing, using a control circuit coupled to a target sub-component of a functional unit of a processor, a utilization of the target sub-component based on a workload that is input into the target sub-component, wherein the target sub-component corresponds to one of a plurality of pipelines executing in parallel;
detecting that the utilization is outside a desired utilization range for the workload; and
throttling at least one sub-component of the functional unit to shut off the one of the plurality of pipelines.

### Claim 14 (depends on 13)

The method of claim 13, wherein the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component.

### Claim 15 (depends on 13)

The method of claim 13, wherein the workload corresponds to a minimal workload and the at least one sub-component corresponds to the target sub-component.

### Claim 16 (depends on 13)

The method of claim 13, wherein:
the target sub-component corresponds to a micro-operation cache for storing predecoded instructions;
the functional unit further comprises at least a first pipeline and a second pipeline each comprising sub-components for providing predecoded instructions to the micro-operation cache; and
the at least one sub-component corresponds to at least one of the first and second pipelines.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
detecting, using a higher-level control circuit coupled to the control circuit, the throttling of the at least one sub-component of the functional unit, wherein the higher-level control circuit is further coupled to a second control circuit that is coupled to a second target sub-component of a second functional unit of the processor; and
coordinating, using the higher-level control circuit, throttling of sub-components by the control circuit and the second control circuit.

### Claim 18

A system comprising:
a physical memory; and
at least one physical processor comprising:
a functional unit comprising at least one sub-component including a target sub-component, wherein the target sub-component corresponds to one of a plurality of pipelines executing in parallel;
a control circuit coupled to the target sub-component and configured to:
observe a workload and a utilization of the target sub-component;
detect that the utilization is outside a desired utilization range for the workload; and
throttle at least one sub-component of the functional unit to shut off the one of the plurality of pipelines.

### Claim 19 (depends on 18)

The system of claim 18, wherein the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component.

### Claim 20 (depends on 18)

The system of claim 18, wherein:
the target sub-component corresponds to a micro-operation cache for storing predecoded instructions;
the functional unit further comprises at least a first pipeline and a second pipeline each comprising sub-components for providing predecoded instructions to the micro-operation cache; and
the at least one sub-component corresponds to at least one of the first and second pipelines.
