# US 12,222,792 B2 · Systems and methods for optimizing battery life in information handling systems using intelligence implemented in storage systems

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- Number: US 12,222,792 B2
- Document ID: US12222792B2
- Status: Granted
- Kind: B2
- Application number: 18/110,724
- Filed: 2023-02-16
- Published: 2024-08-22
- Granted: 2025-02-11
- Earliest claimed: 2023-02-16
- Assignees: Dell Products L.P.
- Applicants: Dell Products L.P.
- Inventors: Min Thu Aung; Wenhua Li; Chai Im Teoh
- Web page: https://patentgrep.com/patent/US12222792B2

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)}
- G06F 1/3212: Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
- G06F 1/3225: of memory devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods are provided that may be implemented to dynamically change the solid state drive (SSD) power and peripheral component interconnect express (PCIe) link state transition time for solid state drive for SSD operation based on current remaining battery power capacity during a battery-only power mode of an information handling system. In one example, an intelligent algorithm in software and SSD firmware may be implemented that will dynamically change the SSD power and PCIe link state transition based on current remaining battery power capacity during battery-only power mode of an information handling system. In this way additional power saving may be realized when current remaining battery power capacity is low during a battery-only power mode so as to extend the battery life for an information handling system.

## Claims

### Claim 1

A method, comprising operating an information handling system having power-consuming circuitry that is coupled to selectably receive power from an external power source or from one or more internal battery cells of a battery system of the information handling system, the power-consuming circuitry comprising at least one first programmable integrated circuit coupled to a solid state drive (SSD) by a peripheral component interconnect express (PCIe) link; where the method further comprises:
determining if a current value of a remaining battery capacity of the battery cells is less than or equal to a predefined low battery capacity threshold value while the power-consuming circuitry is currently receiving power only from the internal battery cells of the battery system, and then:
operating the SSD in a low battery SSD power mode if the current value of the remaining battery capacity of the battery cells is determined to be less than or equal to the predefined low battery capacity threshold value while the external power source is not providing external power to the power-consuming circuitry of the information handling system, and
operating the SSD in a default SSD power mode if the current value of the remaining battery capacity of the battery cells is determined to be greater than the predefined low battery capacity threshold value or if the external power source is providing external power to the power-consuming circuitry of the information handling system; and
where the low battery SSD power mode comprises first peripheral component interconnect express (PCIe) link power management settings and first non-volatile memory express (NVMe) power settings, and where the operating the SSD in the low battery SSD power mode comprises operating the SSD using the first peripheral component interconnect express (PCIe) link power management settings and the first non-volatile memory express (NVMe) power settings;
where the default SSD power mode comprises different and second peripheral component interconnect express (PCIe) link power management settings and second non-volatile memory express (NVMe) power settings, and where the operating the SSD in the default SSD power mode comprises operating the SSD using the second peripheral component interconnect express (PCIe) link power management settings and the second non-volatile memory express (NVMe) power settings;
where the power-consuming circuitry consumes greater power when the SSD operates in the default SSD power mode than when the SSD operates in the low battery SSD power mode; and
where the first NVMe power settings comprise a first value of Idle Time Prior to Transit (ITPT) that is less than a second value of ITPT of the second NVMe power settings.

### Claim 2 (depends on 1)

The method of claim 1, further comprising then iteratively repeating the determining and operating the SDD in the low battery SSD power mode or the default SSD power mode in each given iteration according to the results of the determining of the given iteration.

### Claim 3 (depends on 1)

The method of claim 1, where the at least one first programmable integrated circuit comprises a host programmable integrated circuit executing a host operating system and/or one or more user applications; and where the method further comprises:
responding, in the SSD, to input/output (I/O) data requests received from the host programmable integrated circuit while the SSD is operating in the low battery SSD power mode and while the SSD is operating in the default SSD power mode.

### Claim 4 (depends on 1)

The method of claim 1, where the information handling system further comprises an out-of-band programmable integrated circuit, a battery system programmable integrated circuit, and a SSD programmable integrated circuit; and where the method further comprises:
receiving, in the out-of-band programmable integrated circuit, the real time value of the remaining battery capacity of the battery cells directly from the battery system programmable integrated circuit;
then using the out-of-band programmable integrated circuit to perform the determining if the received real time value of the remaining battery capacity of the battery cells is less than or equal to the predefined low battery capacity threshold value;
then using the out-of-band programmable integrated circuit to transmit a power mode command directly to the SSD programmable integrated circuit based on the results of the determining if the real time value of the remaining battery capacity of the battery cells is less than or equal to the predefined low battery capacity threshold value, the power mode command being a command to operate the SSD in the low battery SSD power mode or a command to operate the SSD in the default SSD power mode;
then receiving the transmitted power mode command in the SSD programmable integrated circuit; and
then using the SSD programmable integrated circuit to respond to the received power mode command by performing the operating the SSD in the low battery SSD power mode if the power mode command is a command to operate the SSD in the low battery SSD power mode, and operating the SSD in the default SSD power mode if the command is a command to operate the SSD in the default SSD power mode.

### Claim 5 (depends on 4)

The method of claim 4, where the out-of-band programmable integrated circuit is a microcontroller integrated within an embedded controller (EC), where the battery system programmable integrated circuit is a microcontroller integrated within a battery management unit (BMU) of the battery system, and where the SSD programmable integrated circuit is a microcontroller integrated within the SSD.

### Claim 6 (depends on 5)

The method of claim 5, where the information handling system further comprises a system management bus (SMBus), and where the EC, BMU and SSD are coupled together in direct data communication with each other by the SMBus.

### Claim 7 (depends on 1)

The method of claim 1, where the information handling system is a notebook computer; and where the battery system is a smart battery pack.

### Claim 8 (depends on 1)

The method of claim 1, where the first PCIe link power management settings comprise a first SSD idle timeout value that is less than a second SSD idle timeout value of the second PCIe link power management settings.

### Claim 9 (depends on 8)

The method of claim 8, where the first PCIe link power management settings further comprise a first value of low battery latency tolerance request (LTR) that is either not required or that is greater than a second value of low battery latency tolerance 33. (LTR) of the second PCIe link power management settings.

### Claim 10 (depends on 1)

The method of claim 1, where the real time value of the remaining battery capacity of the battery cells is state of charge (SOC) of the battery cells.

### Claim 11 (depends on 10)

The method of claim 10, where the predefined low battery capacity threshold value is a low battery SOC condition; and where the method further comprises: automatically suspending SSD I/O data pattern detection counters during the low battery SSD power mode, and automatically resuming the SSD I/O data pattern detection counters after the SSD exits from the low battery SSD power mode and a SOC of the battery cells SOC is not in the low battery SOC condition.

### Claim 12 (depends on 1)

The method of claim 1, further comprising dynamically reducing a PCIe non-volatile memory express (NVMe) SSD self-idle timer value when operating the SSD in the low battery SSD power mode.

### Claim 13

An information handling system, comprising:
a solid state drive (SSD);
a battery system comprising one or more internal battery cells;
power-consuming circuitry that comprises at least one first programmable integrated circuit coupled to the SSD by a peripheral component interconnect express (PCIe) link, the power-consuming circuitry being coupled to selectably receive power from an external power source or from the one or more internal battery cells of the battery system; and
at least one second programmable integrated circuit programmed to determine if a current value of a remaining battery capacity of the battery cells is less than or equal to a predefined low battery capacity threshold value while the power-consuming circuitry is currently receiving power only from the internal battery cells of the battery system, and then:
operate the SSD in a low battery SSD power mode if the current value of the remaining battery capacity of the battery cells is determined to be less than or equal to the predefined low battery capacity threshold value while the external power source is not providing external power to the power-consuming circuitry of the information handling system, and
operate the SSD in a default SSD power mode if the current value of the remaining battery capacity of the battery cells is determined to be greater than the predefined low battery capacity threshold value or if the external power source is providing external power to the power-consuming circuitry of the information handling system; and
where the low battery SSD power mode comprises first peripheral component interconnect express (PCIe) link power management settings and first non-volatile memory express (NVMe) power settings, and where the at least one second programmable integrated circuit is programmed to operate the SSD in the low battery SSD power mode using the first peripheral component interconnect express (PCIe) link power management settings and the first non-volatile memory express (NVMe) power settings;
where the default SSD power mode comprises different and second peripheral component interconnect express (PCIe) link power management settings and second non-volatile memory express (NVMe) power settings, and where the at least one second programmable integrated circuit is programmed to operate the SSD in the default SSD power mode using the second peripheral component interconnect express (PCIe) link power management settings and the second non-volatile memory express (NVMe) power settings; and
where the power-consuming circuitry consumes greater power when the SSD operates in the default SSD power mode than when the SSD operates in the low battery SSD power mode;
where the first NVMe power settings comprise a first value of Idle Time Prior to Transit (ITPT) that is less than a second value of ITPT of the second NVMe power settings.

### Claim 14 (depends on 13)

The system of claim 13, where the at least one second programmable integrated circuit is programmed to then iteratively repeat the determining and operate the SDD in the low battery SSD power mode or the default SSD power mode in each given iteration according to the results of the determining of the given iteration.

### Claim 15 (depends on 13)

The system of claim 13, where the at least one first programmable integrated circuit comprises a host programmable integrated circuit that executes a host operating system and/or one or more user applications; and where the at least one second programmable integrated circuit is programmed to:
respond, in the SSD, to input/output (I/O) data requests received from the host programmable integrated circuit while the SSD is operating in the low battery SSD power mode and while the SSD is operating in the default SSD power mode.

### Claim 16 (depends on 13)

The system of claim 13, where the at least one second programmable integrated circuit comprises an out-of-band programmable integrated circuit, a battery system programmable integrated circuit, and a SSD programmable integrated circuit that are coupled together in direct data communication with each other; and where:
the out-of-band programmable integrated circuit receives the real time value of the remaining battery capacity of the battery cells directly from the battery system programmable integrated circuit, and is programmed to:
then determine if the received real time value of the remaining battery capacity of the battery cells is less than or equal to the predefined low battery capacity threshold value while the power-consuming circuitry is currently receiving power only from the internal battery cells of the battery system;
then transmit a power mode command directly to the SSD programmable integrated circuit based on the results of the determining if the real time value of the remaining battery capacity of the battery cells is less than or equal to the predefined low battery capacity threshold value, the power mode command being a command to operate the SSD in the low battery SSD power mode or a command to operate the SSD in the default SSD power mode;
the SSD programmable integrated circuit receives the power mode command directly from the out-of-band programmable integrated circuit, and is programmed to:
respond to the received power mode command by performing the operating the SSD in the low battery SSD power mode if the power mode command is a command to operate the SSD in the low battery SSD power mode, and operating the SSD in the default SSD power mode if the command is a command to operate the SSD in the default SSD power mode.

### Claim 17 (depends on 16)

The system of claim 16, where the out-of-band programmable integrated circuit is a microcontroller integrated within an embedded controller (EC), where the battery system programmable integrated circuit is a microcontroller integrated within a battery management unit (BMU) of the battery system, and where the SSD programmable integrated circuit is a microcontroller integrated within the SSD.

### Claim 18 (depends on 17)

The system of claim 17, where the information handling system further comprises a system management bus (SMBus), and where the EC, BMU and SSD are coupled together in direct data communication with each other by the SMBus.

### Claim 19 (depends on 13)

The system of claim 13, where the information handling system is a notebook computer; and where the battery system is a smart battery pack.

### Claim 20 (depends on 13)

The system of claim 13, where the first PCIe link power management settings comprise a first SSD idle timeout value that is less than a second SSD idle timeout value of the second PCIe link power management settings.

### Claim 21 (depends on 20)

The system of claim 20, where the first PCIe link power management settings further comprise a first value of low battery latency tolerance request (LTR) that is either not required or that is greater than a second value of low battery latency tolerance 33. (LTR) of the second PCIe link power management settings.

### Claim 22 (depends on 13)

The system of claim 13, where the real time value of the remaining battery capacity of the battery cells is state of charge (SOC) of the battery cells.

### Claim 23 (depends on 22)

The system of claim 22, where the predefined low battery capacity threshold value is a low battery SOC condition; and where the at least one second programmable integrated circuit is programmed to: automatically suspend SSD I/O data pattern detection counters during the low battery SSD power mode, and to automatically resume the SSD I/O data pattern detection counters after the SSD exits from the low battery SSD power mode and a SOC of the battery cells SOC is not in the low battery SOC condition.

### Claim 24 (depends on 13)

The system of claim 13, where the at least one second programmable integrated circuit is programmed to dynamically reduce a PCIe non-volatile memory express (NVMe) SSD self-idle timer value when operating the SSD in the low battery SSD power mode.