# US 12,222,747 B2 · Methods and apparatus to facilitate safe startup of a power management unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,747 B2 - Document ID: US12222747B2 - Status: Granted - Kind: B2 - Application number: 18/129,674 - Filed: 2023-03-31 - Published: 2023-10-05 - Granted: 2025-02-11 - Earliest claimed: 2022-04-01 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Michael Zwerg - Web page: https://patentgrep.com/patent/US12222747B2 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/24: Resetting means - H03K 17/22: Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal. ## Claims ### Claim 1 An integrated circuit comprising: a clock generator; processor circuitry to utilize the clock generator after a boot protocol is complete; and power management circuitry including: a first voltage measurement circuit including an output terminal, the first voltage measurement circuit to, after a supply voltage is above a first threshold, output a first logic value at the output terminal of the first voltage measurement circuit; a second voltage measurement circuit including an input terminal and an output terminal, the second voltage measurement circuit to, after a first voltage at the input terminal of the second voltage measurement circuit corresponds to the first logic value and the supply voltage is above a second threshold, output the first logic value to the output terminal of the second voltage measurement circuit; and a voltage regulator including an input terminal, a first output terminal, and a second output terminal, the voltage regulator to regulate the supply voltage to produce a second voltage; and a third voltage measurement circuit to, after a third voltage at the input terminal of the voltage regulator corresponds to the first logic value and the second voltage is above a third threshold, enable the clock generator, the boot protocol to be complete after the clock generator is enabled. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the second voltage measurement circuit is to output the first logic value at the output terminal of the second voltage measurement circuit when the first voltage at the input terminal of the second voltage measurement circuit corresponds to the first logic value for more than a threshold amount of time. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the boot protocol is complete after a threshold number of pulses from the clock generator. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further including force power-on reset circuitry to reset the first voltage measurement circuit based on an error corresponding to the second voltage measurement circuit. ### Claim 5 (depends on 1) The integrated circuit of claim 1, further including shutdown circuitry to disable the first voltage measurement circuit, the second voltage measurement circuit, the voltage regulator, and the clock generator in response to a request. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the first voltage measurement circuit includes an input terminal, further including a fourth voltage measurement circuit to output the first logic value to the input terminal of the first voltage measurement circuit after the supply voltage is above a fourth threshold, the first voltage measurement circuit to output the first logic value at the output terminal of the first voltage measurement circuit after a fourth voltage at the input terminal of the first voltage measurement circuit corresponds to the first logic value. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the processor circuitry is powered using the second voltage. ### Claim 8 (depends on 1) The integrated circuit of claim 1, further including a flip-flop to hold an output of the voltage regulator, the output to enable the clock generator. ### Claim 9 An integrated circuit comprising: first voltage measurement circuitry including an input terminal and an output terminal; second voltage measurement circuitry including: delay circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the first voltage measurement circuitry; a logic gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic gate coupled to the output terminal of the first voltage measurement circuitry, the second input terminal coupled to the output terminal of the delay circuitry; and a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal, and the output terminal of the comparator coupled to the third input terminal of the logic gate; a regulator including an input terminal and an output terminal, the input terminal of the regulator coupled to the output terminal of the logic gate; and a clock generator including an input terminal coupled to the output terminal of the regulator. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the logic gate is a first logic gate, further including a second logic gate and a third logic gate, wherein: the input terminal of the delay circuitry and the first input terminal of the first logic gate is coupled to the first voltage measurement circuitry via the second logic gate; and the output terminal of the first logic gate is coupled to regulator via the third logic gate. ### Claim 11 (depends on 9) The integrated circuit of claim 9, wherein the logic gate is a first logic gate, further including: a flip-flop; and a second logic gate, the input terminal of the clock generator coupled to the output terminal of the regulator via the flip-flop and the second logic gate. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein: the flip-flop includes an input terminal and an output terminal, the input terminal of the flip-flop coupled to the output terminal of the regulator; and the second logic gate includes an input terminal and an output terminal, the input terminal of the first logic gate coupled to the output terminal of the flip-flop, the output terminal of the first logic gate coupled to the input terminal of the clock generator. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the first logic gate is an AND gate and the second logic gate is a NOT gate. ### Claim 14 (depends on 12) The integrated circuit of claim 12, wherein the output terminal of the flip-flop is coupled to the input terminal of the delay circuitry and the first input terminal of the first logic gate. ### Claim 15 An apparatus comprising: an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal. ### Claim 16 (depends on 15) The apparatus of claim 15, further including a first logic gate and a second logic gate, the input terminal coupled to the first logic gate and the output terminal coupled to the second logic gate. ### Claim 17 (depends on 16) The apparatus of claim 16, further including a voltage regulator including an input terminal and an output terminal, the input terminal of the voltage regulator coupled to the output terminal. ### Claim 18 (depends on 17) The apparatus of claim 17, further including a flip-flop, the output terminal of the voltage regulator coupled to the input terminal via the flip-flop and the first logic gate. ### Claim 19 (depends on 18) The apparatus of claim 18, further including an oscillator coupled to the flip-flop. ### Claim 20 (depends on 16) The apparatus of claim 16, wherein the logic AND gate is a first logic AND gate, wherein the first logic gate is at least one of a second logic AND gate or a logic OR gate.