# US 12,222,612 B2 · Array substrate, display panel, and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,612 B2 - Document ID: US12222612B2 - Status: Granted - Kind: B2 - Application number: 17/789,141 - Filed: 2021-05-13 - Published: 2023-03-23 - Granted: 2025-02-11 - Earliest claimed: 2020-06-28 - Assignees: Hefei Boe Display Technology Co., Ltd.; BOE Technology Grooup Co., Ltd. - Applicants: Hefei BOE Display Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Chunxu Zhang; Yuntian Zhang; Xiaoting Jiang; Haipeng Yang; Ke Dai - Web page: https://patentgrep.com/patent/US12222612B2 ## CPC - G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)} - G02F 1/133388: {with constructional differences between the display region and the peripheral region} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G09G 3/3677: {suitable for active matrices only} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133512: {Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence)} - G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} - G09G 3/3674: {Details of drivers for scan electrodes} - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate. ## Claims ### Claim 1 An array substrate, comprising: a base substrate, comprising a display region and a peripheral region surrounding the display region; a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction; a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, the first direction being intersected with the second direction; a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate, wherein the clock lead further comprises a second clock lead, wherein the compensation capacitor plate connected to the second clock lead comprises a first segment and a second segment that are connected sequentially in the first direction, a width of the first segment and a width of the second segment being different in the second direction, and a length of the second clock lead being less than a length of the first clock lead. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein the clock lead comprises a first clock lead, and the compensation capacitor plate connected to the first clock lead is strip-shaped. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein the strip-shaped compensation capacitor plate extends in the first direction. ### Claim 4 (depends on 3) The array substrate according to claim 3, wherein a distance between two compensation capacitor plates connected to two adjacent first clock leads is greater than a width of the strip-shaped compensation capacitor plate. ### Claim 5 (depends on 1) The array substrate according to claim 1, wherein an orthographic projection, on the base substrate, of the compensation capacitor plate is within an orthographic projection, on the base substrate, of the clock line connected to the compensation capacitor plate. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein a minimum distance between an orthographic projection, on the base substrate, of the compensation capacitor plate and an orthographic projection, on the base substrate, of another clock lead is greater than a first threshold, wherein the another clock lead is not connected to the compensation capacitor plate. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein the plurality of clock leads are arranged in the first direction and organized into a plurality of cycles, and the clock leads in each of the cycles are arranged sequentially in an ascending order in terms of length. ### Claim 8 (depends on 7) The array substrate according to claim 7, wherein the compensation capacitor plate connected to two shortest clock leads in the each of the cycles comprises a first segment and a second segment that are connected sequentially in the first direction, a width of the first segment and a width of the second segment being different in the second direction. ### Claim 9 (depends on 1) The array substrate according to claim 1, wherein each clock lead is connected to the compensation capacitor plate by a plurality of first via holes. ### Claim 10 (depends on 1) The array substrate according to claim 1, further comprising: a pixel electrode, disposed on the base substrate and in the display region; and the compensation capacitor plate and the pixel electrode are in a same layer. ### Claim 11 (depends on 9) The array substrate according to claim 9, wherein each clock lead is connected to the corresponding clock line by a third via hole. ### Claim 12 (depends on 9) The array substrate according to claim 9, wherein each clock lead is connected to the compensation capacitor plate by a third via hole, and the first via hole and the third via hole is formed in a one-time patterning process. ### Claim 13 (depends on 1) The array substrate according to claim 1, further comprising: a signal line of another type, disposed on the base substrate and in the peripheral region, wherein the signal line extends in the first direction, and the clock line is disposed between the signal line and the shift register unit. ### Claim 14 (depends on 1) The array substrate according to claim 1, further comprising: an interdigital connection block, wherein one end of the clock lead is connected to the compensation capacitor plate by the connection block; and in the first direction, a width of the connection block is greater than a width of the clock lead. ### Claim 15 (depends on 14) The array substrate according to claim 14, wherein the connection block comprises a connection block body and a plurality of bumps connected to the connection block body, and the connection block is connected to a first via hole by the plurality of bumps, thereby being connected to the compensation capacitor plate. ### Claim 16 (depends on 1) The array substrate according to claim 1, wherein part of the plurality of clock leads are connected to middle portions of the compensation capacitor plates, and another part of the plurality of the clock leads are connected to end portions of the compensation capacitor plates. ### Claim 17 A display panel, comprising: an array substrate; and a color film substrate, cell-assembled with the array substrate, wherein the array substrate comprises: a base substrate, comprising a display region and a peripheral region surrounding the display region; a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction; a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, the first direction being intersected with the second direction; a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate, wherein the clock lead further comprises a second clock lead, wherein the compensation capacitor plate connected to the second clock lead comprises a first segment and a second segment that are connected sequentially in the first direction, a width of the first segment and a width of the second segment being different in the second direction, and a length of the second clock lead being less than a length of the first clock lead. ### Claim 18 (depends on 17) The display panel according to claim 17, wherein the color film substrate comprises a metal light-shielding layer; wherein the metal light-shielding layer and each of the compensation capacitor plate, the clock lead, and the clock line form a capacitor; and a sum of a capacitance between the compensation capacitor plate and the metal light-shielding layer and a capacitance between the metal light-shielding layer and the clock lead connected to the compensation capacitor plate is within a first capacitance range, a difference between an upper limit and a lower limit of the first capacitance range being less than a second threshold. ### Claim 19 A display apparatus, comprising a display panel which comprises: an array substrate; and a color film substrate, cell-assembled with the array substrate, wherein the array substrate comprises: a base substrate, comprising a display region and a peripheral region surrounding the display region; a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction; a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, the first direction being intersected with the second direction; a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate, wherein the clock lead further comprises a second clock lead, wherein the compensation capacitor plate connected to the second clock lead comprises a first segment and a second segment that are connected sequentially in the first direction, a width of the first segment and a width of the second segment being different in the second direction, and a length of the second clock lead being less than a length of the first clock lead.