# US 12,222,545 B2 · Package and method of forming same

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- Number: US 12,222,545 B2
- Document ID: US12222545B2
- Status: Granted
- Kind: B2
- Application number: 18/302,046
- Filed: 2023-04-18
- Published: 2023-08-24
- Granted: 2025-02-11
- Earliest claimed: 2019-11-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Hsuan Tai; Chung-Ming Weng; Hung-Yi Kuo; Cheng-Chieh Hsieh; Hao-Yi Tsai; Chung-Shi Liu; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US12222545B2

## CPC

- G02B 6/13: Integrated optical circuits characterised by the manufacturing method
- G02B 6/12002: {Three-dimensional structures}
- G02B 6/12004: {Combinations of two or more optical elements}
- G02B 6/30: for use between fibre and thin-film device
- G02B 6/4214: {the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence)}
- G02B 6/424: {Mounting of the optical light guide}
- G02B 6/4249: {comprising arrays of active devices and fibres}
- G02B 6/43: Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/01: Manufacture or treatment
- H10W 90/00: Package configurations
- G02B 6/4232: {using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072)}
- G02B 2006/12147: {Coupler}
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.

## Claims

### Claim 1

A method comprising:
attaching a photonic integrated circuit die to a carrier substrate, the photonic integrated circuit die comprising an optical coupler and an insulting layer over the optical coupler;
forming a first opening through the insulating layer;
forming an encapsulant over the carrier substrate and the photonic integrated circuit die, the encapsulant extending along a sidewall of the photonic integrated circuit die;
after forming the encapsulant, forming a first redistribution structure over the photonic integrated circuit die and the encapsulant, wherein forming the first redistribution structure comprises:
forming a first dielectric layer over the encapsulant and the photonic integrated circuit die; and
after forming the first dielectric layer, forming a conductive line over the first dielectric layer, the conductive line extending through the first dielectric layer; and
after forming the first redistribution structure, patterning the first redistribution structure to form a second opening in the first redistribution structure, the second opening extending through the first opening in the insulating layer and exposing the optical coupler.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, before attaching the photonic integrated circuit die to the carrier substrate, forming a second redistribution structure over the carrier substrate.

### Claim 3 (depends on 2)

The method of claim 2, further comprising, before attaching the photonic integrated circuit die to the carrier substrate, forming a through via over the second redistribution structure.

### Claim 4 (depends on 1)

The method of claim 1, further comprising coupling an optical fiber to the optical coupler.

### Claim 5 (depends on 1)

The method of claim 1, wherein the optical coupler is an edge coupler.

### Claim 6 (depends on 1)

The method of claim 1, wherein the optical coupler is a grating coupler.

### Claim 7 (depends on 1)

The method of claim 1, wherein the photonic integrated circuit die comprises die connectors, the insulating layer extending along sidewalls of the die connectors.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a sacrificial layer in the first opening, wherein forming the second first opening comprises removing the sacrificial layer.

### Claim 9

A method of forming a semiconductor device, the method comprising:
forming a first redistribution structure on a carrier substrate, the first redistribution structure comprising a first metallization pattern;
attaching a photonic integrated circuit die to the first redistribution structure, the photonic integrated circuit die comprising an optical coupler, an insulating layer over the optical coupler, and a sacrificial layer extending through the insulating layer, the sacrificial layer being over the optical coupler;
forming an encapsulant on the first redistribution structure and along sidewalls of the photonic integrated circuit die;
after forming the encapsulant, forming a second redistribution structure on the encapsulant, forming the second redistribution structure comprising:
forming a first dielectric layer over the encapsulant and the photonic integrated circuit die; and
after forming the first dielectric layer, forming a second metallization pattern over the first dielectric layer; and
after forming the second redistribution structure, forming an opening through the second redistribution structure above the optical coupler.

### Claim 10 (depends on 9)

The method of claim 9, wherein the photonic integrated circuit die comprises die connectors, wherein the insulating layer extends along sidewalls of the die connectors.

### Claim 11 (depends on 10)

The method of claim 10, further comprising removing the sacrificial layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein removing the sacrificial layer is performed prior to forming the second redistribution structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the opening exposes an upper surface of the insulating layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein forming the opening comprises exposing sidewalls of the insulating layer.

### Claim 15

A method of forming a semiconductor device, the method comprising:
forming a first redistribution structure on a carrier substrate, the first redistribution structure comprising a first metallization pattern;
forming through vias on the first redistribution structure;
attaching a photonic integrated circuit die to the first redistribution structure, the photonic integrated circuit die comprising an optical coupler, wherein the photonic integrated circuit die comprises die connectors and a first insulating layer along sidewalls of the die connectors;
forming an encapsulant on the first redistribution structure and along sidewalls of the photonic integrated circuit die, an upper surface of the photonic integrated circuit die being level with an upper surface of the encapsulant;
forming a first opening in the photonic integrated circuit die to expose the optical coupler;
forming a second redistribution structure on the encapsulant, the second redistribution structure extending into the first opening, the second redistribution structure comprising a second metallization pattern; and
forming a second opening through the second redistribution structure, the second opening exposing the photonic integrated circuit die.

### Claim 16 (depends on 15)

The method of claim 15, wherein the photonic integrated circuit die comprises a sacrificial layer extending through the first insulating layer, the sacrificial layer being over the optical coupler, wherein forming the first opening comprises removing the sacrificial layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the second redistribution structure comprises:
forming a second insulating layer over the die connectors and in the first opening; and
forming the second metallization pattern to extend through the second insulating layer to contact a first die connector of the die connectors.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second insulating layer completely fills the first opening.

### Claim 19 (depends on 16)

The method of claim 16, wherein the second opening exposes an upper surface of the first insulating layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
forming a first external connector and a second external connector, wherein the first external connector is between the second opening and a closest edge of the second redistribution structure.