# US 12,222,390 B2 · Fault tolerant synchronizer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,222,390 B2
- Document ID: US12222390B2
- Status: Granted
- Kind: B2
- Application number: 18/457,537
- Filed: 2023-08-29
- Published: 2023-12-14
- Granted: 2025-02-11
- Earliest claimed: 2018-10-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Denis Roland Beaudoin; Samuel Paul Visalli
- Web page: https://patentgrep.com/patent/US12222390B2

## CPC

- G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals}
- H03K 19/0033: {Radiation hardening}
- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- H03K 3/037: Bistable circuits
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

## Claims

### Claim 1

A synchronization circuit, comprising:
a first synchronizer having a first data input, a first clock input, and first output;
a second synchronizer having a second data input, a second clock input, and a second output;
selection circuitry having first, second, and third inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively;
the selection circuitry further including storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to an internal input of the selection circuitry.

### Claim 2 (depends on 1)

The synchronization circuit of claim 1, wherein the selection circuitry includes exclusive-OR logic circuitry having the first and second inputs, and a logic output.

### Claim 3 (depends on 2)

The synchronization circuit of claim 2, wherein the selection circuitry further includes multiplexing circuitry having the third input, the internal input, and the synchronized data output.

### Claim 4 (depends on 1)

The synchronization circuit of claim 1, wherein the storage circuitry includes soft error protection circuitry having the storage data input, the third clock input, and the feedback output.

### Claim 5 (depends on 1)

The synchronization circuit of claim 1, further comprising soft error detection circuitry coupled to the first and second outputs of the first and second synchronizers, respectively, the soft error detection circuitry having a soft error output.

### Claim 6 (depends on 5)

The synchronization circuit of claim 5, further comprising test circuitry coupled to the soft error detection circuitry.

### Claim 7 (depends on 6)

The synchronization circuit of claim 6, wherein the soft error detection circuitry includes an input multiplexer coupled to the first and second outputs of the first and second synchronizers, respectively, and also coupled to the testing circuitry.

### Claim 8 (depends on 7)

The synchronization circuit of claim 7, wherein the soft error detection circuitry further includes comparison circuitry coupled to the input multiplexer.

### Claim 9 (depends on 8)

The synchronization circuit of claim 8, wherein the soft error detection circuitry further includes sequence storage coupled to the comparison circuitry.

### Claim 10

A circuit, comprising:
source circuitry;
first flip-flop circuitry having a first input and a first output, the first input coupled to the source circuitry;
destination circuitry;
second flip-flop circuitry having a second input and a second output, the second input coupled to the destination circuitry; and
synchronization circuitry having third and fourth inputs and third and fourth outputs, the third input coupled to the first output, the fourth input coupled to the second output, the third output coupled to the destination circuitry, and the fourth output coupled to the source circuitry.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein the synchronization circuitry includes a first synchronization circuit having the third input and the third output, and a second synchronization circuit having the fourth input and the fourth output.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein each of the first and second synchronization circuits includes:
first and second synchronizers;
selection circuitry coupled to the first and second synchronizers, wherein the selection circuitry includes storage circuitry and a feedback loop having an output coupled to the storage circuitry.

### Claim 13 (depends on 11)

The circuit of claim 11, wherein the first synchronization circuit is configured to receive a clock signal and synchronize an output signal of the first flip-flop circuitry to the clock signal.

### Claim 14 (depends on 11)

The circuit of claim 11, wherein the second synchronization circuit is configured to receive a clock signal and synchronize an output signal of the second flip-flop circuitry to the clock signal.

### Claim 15 (depends on 11)

The circuit of claim 11, further comprising:
first AND logic circuitry having inputs coupled to the source circuitry and an output coupled to the first input of the first synchronization circuit; and
second AND logic circuitry having inputs coupled to the destination circuitry and an output coupled to the second input of the second flip-flop circuitry.

### Claim 16 (depends on 15)

The circuit of claim 15, further comprising:
exclusive-OR logic circuitry having one input coupled to the output of the first AND logic circuitry, and another input coupled to the first output of the first flip-flop circuitry and the third input of the first synchronization circuit to form a first feedback loop; and
second exclusive-OR logic circuitry having one input coupled to the output of the second AND logic circuitry, and another input coupled to the second output of the second flip-flop circuitry and the fourth input of the second synchronization circuit to form a second feedback loop.

### Claim 17 (depends on 16)

The circuit of claim 16, further comprising:
exclusive-NOR logic circuitry having one input coupled to the fourth output of the second synchronization circuit and another input coupled to the first feedback loop.

### Claim 18 (depends on 17)

The circuit of claim 17, further comprising:
third exclusive-OR logic circuitry having one input coupled to the third output of the first synchronization circuit and another input coupled to the second feedback loop.