# US 12,222,389 B2 · Test board for testing memory signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,389 B2 - Document ID: US12222389B2 - Status: Granted - Kind: B2 - Application number: 17/662,368 - Filed: 2022-05-06 - Published: 2023-03-30 - Granted: 2025-02-11 - Earliest claimed: 2021-09-27 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Honglong Shi; Maosong Ma - Web page: https://patentgrep.com/patent/US12222389B2 ## CPC - G01R 1/0408: {Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets (G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808)} - G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)} - G11C 29/56016: {Apparatus features} - G11C 2029/5602: {Interface to device under test} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A test board for testing a memory signal includes a first surface and a second surface. The first surface of the test board comprises a raised region and a non-raised region. The raised region is provided with a first connection area connectable to a main board, and a level at which the raised is located is higher than a level at which the non raised region is located by a preset value. The second surface of the test board includes a test area and a second connection area connectable to a memory chip. The test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area. ## Claims ### Claim 1 A test board for testing a memory signal, comprising a first surface and a second surface, wherein the first surface of the test board comprises a raised region and a non raised region; wherein the raised region is provided with a first connection area connectable to a main board, and a level at which the non raised region is located is higher than a level at which the non raised region is located by a preset value; wherein the second surface of the test board comprises a test area and a second connection area connectable to a memory chip; wherein the test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area. ### Claim 2 (depends on 1) The test board of claim 1, wherein the test area comprises at least two sub-test areas on two sides of the second connection area, the at least two sub-test areas having a same number of test points. ### Claim 3 (depends on 2) The test board of claim 2, wherein the second connection area is a square area, the at least two sub-test areas comprise a first sub-test area and a second sub-test area, and the first sub-test area and the second sub-test area are disposed along two long sides of the second connection area respectively. ### Claim 4 (depends on 1) The test board of claim 1, wherein the test area is provided with test points, a number of the test points of the test area being the same as a number of function pins of the memory chip; wherein the main board comprises a third connection area connectable to the first connection area, the third connection area is provided with first connection points connectable to the function pins of the memory chip, and the first connection area is provided with second connection points at positions for connecting the first connection points; and wherein each of first connection lines in the first connection harness is bridged between a respective one of the second connection points and a respective one of the test points corresponding to the respective second connection point. ### Claim 5 (depends on 4) The test board of claim 4, wherein the second connection area is provided with third connection points at positions for connecting the pins of the memory chip; and wherein each of second connection lines in the second connection harnesses is bridged between a respective one of the third connection points and a respective one of the test points corresponding to the respective third connection point. ### Claim 6 (depends on 4) The test board of claim 4, wherein two adjacent first connection lines in the first connection harness are insulated from each other; two adjacent second connection lines in the second connection harness are insulated from each other; and the first connection lines have a segment parallel to a segment of the second connection lines. ### Claim 7 (depends on 6) The test board of claim 6, wherein the segment of the first connection lines is equal in length to the segment of the second connection lines. ### Claim 8 (depends on 6) The test board of claim 6, wherein a distance between the segment of the first connection lines and the segment of the second connection lines is greater than or equal to a first distance threshold. ### Claim 9 (depends on 4) The test board of claim 4, wherein the memory chip comprises function pins with different functions; the first connection lines comprise first sub-connection lines corresponding to different functions; and the second connection lines comprise second sub-connection lines corresponding to different functions; wherein for each of the functions, a first sub-connection line corresponding to the function is bridged between a second connection point corresponding to the function and a test point corresponding to the function; and wherein for each of the functions, a second sub-connection line corresponding to the function is bridged between a third connection point corresponding to the function and a test point corresponding to the function, to enable a corresponding function signal of the memory chip to be tested based on the test point corresponding to the function. ### Claim 10 (depends on 1) The test board of claim 1, wherein in response to a number of test points provided on the test area being smaller than a number of function pins of the memory chip, the test board is further provided with a third connection harness for connecting the first connection area and the second connection area. ### Claim 11 (depends on 1) The test board of claim 1, wherein the test area comprises at least two sub-test areas, each of the at least two sub-test areas being provided with an array of test points with an equal row spacing and an equal column spacing. ### Claim 12 (depends on 1) The test board of claim 1, wherein the preset value is 2.5 mm.