# US 12,222,388 B2 · Integrated communication link testing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,388 B2 - Document ID: US12222388B2 - Status: Granted - Kind: B2 - Application number: 18/488,936 - Filed: 2023-10-17 - Published: 2024-02-08 - Granted: 2025-02-11 - Earliest claimed: 2018-06-14 - Assignees: Tektronix, Inc. - Applicants: Tektronix, Inc. - Inventors: Pirooz Hojabri; Joshua J. O'Brien; Gregory A. Martin; Patrick Satarzadeh; Karen Hovakimyan - Web page: https://patentgrep.com/patent/US12222388B2 ## CPC - G01R 31/3167: Testing of combined analog and digital circuits {(testing ADC's H03M1/1071)} - G01R 31/3171: {BER [Bit Error Rate] test} - G01R 31/2841: {Signal generators} - G01R 31/3187: Built-in tests - G01R 31/31905: {Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture} - G01R 31/31716: {Testing of input or output with loop-back} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared. ## Claims ### Claim 1 A test and measurement device, comprising: an input configured to receive an analog signal from a Device Under Test (DUT); an input signal conditioner coupled to the input and structured to perform signal conditioning on the analog signal to produce a conditioned analog signal; and a receiver coupled to the input signal conditioner, the receiver including an Analog to Digital Converter (ADC) structured to convert the conditioned analog signal to a digital signal, and a digital processor structured to accept the digital signal and perform signal conditioning, symbol recovery, and analysis on the digital signal at a rate that is the same or exceeds a baud rate of the analog signal. ### Claim 2 (depends on 1) The test and measurement device according to claim 1, in which the input and input signal conditioner are in a housing separate from the receiver and physically attached to the DUT. ### Claim 3 (depends on 1) The test and measurement device according to claim 1, in which the input and input signal conditioner are structured to receive an optical signal from the DUT, the input signal conditioner further comprising an optical receiver and an optical-to-electrical converter. ### Claim 4 (depends on 1) The test and measurement device according to claim 1, in which the input signal conditioner is included within the receiver. ### Claim 5 (depends on 1) The test and measurement device according to claim 1, in which the input signal conditioner includes a bypass mode that causes the conditioned analog signal to be identical to the analog signal. ### Claim 6 (depends on 1) The test and measurement device according to claim 1, in which the input signal conditioner is structured to perform analog Continuous Time Linear Equalization (CTLE) on the input analog signal. ### Claim 7 (depends on 6) The test and measurement device according to claim 6, in which performing Continuous Time Linear Equalization (CTLE) provides signal path bandwidth greater than 100 GHz. ### Claim 8 (depends on 6) The test and measurement device according to claim 6, in which performing Continuous Time Linear Equalization (CTLE) is programmable through a user interface. ### Claim 9 (depends on 6) The test and measurement device according to claim 6, in which performing Continuous Time Linear Equalization (CTLE) provides de-embedding of an input channel in the DUT. ### Claim 10 (depends on 1) The test and measurement device according to claim 1, in which the input signal conditioner is structured to perform differential skew correction. ### Claim 11 A test and measurement device, comprising: a transmitter structured to output an analog output signal, the transmitter including a signal generator structured to generate a base output signal, a digital processor structured to add one or more impairments to the base output signal to form a combined output signal, and a Digital to Analog Converter (DAC) coupled to the digital signal processor and structured to convert the combined output signal to the output analog signal; an output signal conditioner coupled to the transmitter and structured to perform signal conditioning on the output analog signal to produce a conditioned output analog signal; and an output structured to convey the conditioned output analog signal to a Device Under Test (DUT). ### Claim 12 (depends on 11) The test and measurement device according to claim 11, in which the transmitter includes a jitter impairment generator. ### Claim 13 (depends on 12) The test and measurement device according to claim 12, in which the jitter impairment generator is structured to cause the output analog signal to include at least one of periodic or aperiodic jitter. ### Claim 14 (depends on 12) The test and measurement device according to claim 12, in which the jitter impairment generator is structured to cause the output analog signal to include random jitter. ### Claim 15 (depends on 11) The test and measurement device according to claim 11, in which the transmitter includes a spread spectrum clock generator. ### Claim 16 (depends on 11) The test and measurement device according to claim 11, in which the output signal conditioner is structured to add at least one of differential skew and common mode impairments to the output analog signal to produce the conditioned output analog signal. ### Claim 17 (depends on 11) The test and measurement device according to claim 11, in which the output signal conditioner is structured to add analog signal impairments to the output analog signal to produce the conditioned output analog signal. ### Claim 18 (depends on 11) The test and measurement device according to claim 11, in which the output signal conditioner is structured to add analog crosstalk emulation to the output analog signal to produce the conditioned output analog signal. ### Claim 19 (depends on 11) The test and measurement device according to claim 11, in which the output signal conditioner includes a bypass mode that causes the conditioned output analog signal to be identical to the output analog signal. ### Claim 20 (depends on 11) The test and measurement device according to claim 11, in which the output signal conditioner includes a variable gain attenuator.