# US 12,222,376 B2 · Peak voltage detection circuit with reduced charge loss > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,222,376 B2 - Document ID: US12222376B2 - Status: Granted - Kind: B2 - Application number: 17/815,961 - Filed: 2022-07-29 - Published: 2024-02-01 - Granted: 2025-02-11 - Earliest claimed: 2022-07-29 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GlobalFoundries U.S. Inc. - Inventors: Indranil Som; Vaibhav Anantrai Ruparelia; Kuppireddy Vasudeva Reddy - Web page: https://patentgrep.com/patent/US12222376B2 ## CPC - G01R 19/04: Measuring peak values {or amplitude or envelope} of AC or of pulses - H03K 5/1532: Peak detectors (measuring characteristics of individual pulses G01R29/02) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch. ## Claims ### Claim 1 A circuit structure comprising: a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch, the peak voltage detector coupling the first input node and the second input node to an output node; and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor, wherein the first electrically actuated switch and the second electrically actuated switch are configured in a half-bridge arrangement, and the first electrically actuated switch directly couples the capacitor to the second input node of the peak voltage detector; wherein the input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch. ### Claim 2 (depends on 1) The circuit structure of claim 1, further comprising a skewed buffer coupling the input line to the control node of the first electrically actuated switch and the control node of the second electrically actuated switch. ### Claim 3 (depends on 1) The circuit structure of claim 1, wherein the peak voltage detector includes: a first operational transconductance amplifier coupling the first input node and the second input node to an amplifier output node; a first transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the amplifier output node to a supply voltage; and a second transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the supply voltage to the output node of the peak voltage detector. ### Claim 4 (depends on 1) The circuit structure of claim 1, further comprising a reset transistor having a first source/drain terminal coupled to the second electrically actuated switch, a second source/drain terminal coupled to ground, and a gate terminal coupled to a reset line. ### Claim 5 (depends on 1) The circuit structure of claim 1, further comprising a second operational transconductance amplifier coupling the capacitor to a reference voltage line. ### Claim 6 (depends on 1) The circuit structure of claim 1, wherein the capacitor has a capacitance of at most sixty picofarads (pF) and a voltage droop of at most 230 millivolts (mV). ### Claim 7 (depends on 1) The circuit structure of claim 1, wherein the input line provides a sole input signal transmitted to the peak voltage detector, the control node of the first electrically actuated switch and the control node of the second electrically actuated switch. ### Claim 8 A circuit structure comprising: a peak voltage detector coupling a first input node and a second input node to an output node, wherein the peak voltage detector includes, a first operational transconductance amplifier coupling the first input node and the second input node to an amplifier output node, a first transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the amplifier output node to a supply voltage, and a second transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the supply voltage to the output node of the peak voltage detector; an input line coupled to the first input node of the peak voltage detector; a first electrically actuated switch coupled to the second input node of the peak voltage detector; and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor, wherein the first electrically actuated switch and the second electrically actuated switch each include a respective control node coupled to the input line, such that a signal in the input line enables current flow through the first electrically actuated switch and the second electrically actuated switch. ### Claim 9 (depends on 8) The circuit structure of claim 8, further comprising a skewed buffer coupling the input line to the control node of the first electrically actuated switch and the control node of the second electrically actuated switch. ### Claim 10 (depends on 8) The circuit structure of claim 8, wherein the first electrically actuated switch and the second electrically actuated switch are configured in a half-bridge arrangement. ### Claim 11 (depends on 8) The circuit structure of claim 8, further comprising a reset transistor having a first source/drain terminal coupled to the second electrically actuated switch, a second source/drain terminal coupled to ground, and a gate terminal coupled to a reset line. ### Claim 12 (depends on 8) The circuit structure of claim 8, further comprising a second operational transconductance amplifier coupling the capacitor to a reference voltage line. ### Claim 13 (depends on 8) The circuit structure of claim 8, wherein the capacitor has a capacitance of at most sixty picofarads (pF) and a voltage droop of at most 230 millivolts (mV). ### Claim 14 (depends on 8) The circuit structure of claim 8, wherein the input line provides a sole input signal transmitted to the peak voltage detector, the control node of the first electrically actuated switch, and the control node of the second electrically actuated switch. ### Claim 15 A circuit structure comprising: a peak voltage detector coupling a first input node and a second input node to and an output node; an input line coupled to the first input node of the peak voltage detector; a first electrically actuated switch coupled to the second input node of the peak voltage detector; a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor, wherein the first electrically actuated switch and the second electrically actuated switch are configured in a half-bridge arrangement, and the first electrically actuated switch directly couples the capacitor to the second input node of the peak voltage detector; wherein the first electrically actuated switch and the second electrically actuated switch each include a respective control node coupled to the input line, such that a signal in the input line enables current flow through the first electrically actuated switch and the second electrically actuated switch; a skewed buffer coupling the input line to the control node of the first electrically actuated switch and the control node of the second electrically actuated switch; and a reset transistor having a first source/drain terminal coupled to the second electrically actuated switch, a second source/drain terminal coupled to ground, and a gate terminal coupled to a reset line. ### Claim 16 (depends on 15) The circuit structure of claim 15, wherein the peak voltage detector includes: a first operational transconductance amplifier coupling the first input node and the second input node to an amplifier output node; a first transistor having a gate terminal coupled to the output node, and source/drain terminals coupling the amplifier output node to a supply voltage; and a second transistor having a gate terminal coupled to the amplifier output node, and source/drain terminals coupling the supply voltage to the output node of the peak voltage detector. ### Claim 17 (depends on 16) The circuit structure of claim 16, wherein the supply voltage defines threshold voltage for actuating the first electrically actuated switch and the second electrically actuated switch. ### Claim 18 (depends on 15) The circuit structure of claim 15, further comprising a second operational transconductance amplifier coupling the capacitor to a reference voltage line. ### Claim 19 (depends on 15) The circuit structure of claim 15, wherein the capacitor has a capacitance of at most sixty picofarads (pF) and a voltage droop of at most 230 millivolts (mV). ### Claim 20 (depends on 15) The circuit structure of claim 15, wherein the input line provides a sole input signal transmitted to the peak voltage detector, the control node of the first electrically actuated switch and the control node of the second electrically actuated switch.