Three-dimensional semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsYounghwan Son, Jeehoon Han
Life of this patent
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Abstract
Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.
Claims20
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate;
- an electrode structure on a first region of the substrate, the electrode structure comprising gate electrodes stacked in a first direction that is perpendicular to a top surface of the substrate;
- a first source conductive pattern between the first region of the substrate and the electrode structure;
- a lower sacrificial pattern on a second region of the substrate;
- an insulating layer between the second region of the substrate and the lower sacrificial pattern;
- a buffer insulating layer on the lower sacrificial pattern;
- a vertical semiconductor pattern that penetrates the electrode structure and the first source conductive pattern on the first region of the substrate;
- and
- a dummy vertical pattern that penetrates the buffer insulating layer, the lower sacrificial pattern, and the insulating layer on the second region of the substrate,
- wherein each of the buffer insulating layer and the insulating layer includes an oxide layer.
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate;
- an electrode structure on a first region of the substrate, the electrode structure comprising gate electrodes that are stacked in a first direction that is perpendicular to a top surface of the substrate;
- a first source conductive pattern between the first region of the substrate and the electrode structure;
- a lower sacrificial pattern on a second region of the substrate;
- an insulating layer between the second region of the substrate and the lower sacrificial pattern;
- a buffer insulating layer on the lower sacrificial pattern;
- a vertical semiconductor pattern that penetrates the electrode structure and the first source conductive pattern and extends into the first region of the substrate;
- and
- a dummy vertical pattern that penetrates the buffer insulating layer, the lower sacrificial pattern and the insulating layer and extends into the second region of the substrate,
- wherein the lower sacrificial pattern includes a different material from that of each of the buffer insulating layer and the insulating layer.
Dependencies are inferred from the claim text.