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US 12,219,281 B2Granted
Image sensor, image sensing device including same, and operating method
AssigneeSamsung Electronics Co., Ltd.
InventorsChan Young Jang, Hee Kang, Jong Min You
Life of this patent
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Abstract
An image sensor includes; a pixel array disposed in a Bayer pattern and including pixels which respectively generate electrical charge according to received light incident, and an analog logic configured to convert an analog signal output from at least one pixel among the pixels into a first digital code using analog-to-digital conversion, and convert the first digital code into a second digital code by adjusting low-order bits of the first digital code in response to a control signal.
Claims16
An image sensor comprising:
- a pixel array disposed in a Bayer pattern and including pixels which respectively generate an electrical charge according to incident light;
- and
- an analog logic configured to:
- convert an analog signal output from at least one pixel among the pixels into a first digital code consisting of N-bits using analog-to-digital conversion, where N is a positive integer;
- receive a control signal;
- generate a second digital code consisting of N-k bits by eliminating k low-order bits of the first digital code in response to the control signal, where k is an integer less than N and greater than zero, wherein the N-k bits of the second digital code are the same as N-k high-order bits of the first digital code and k is variably controlled by the control signal,
- wherein the analog logic includes:
- an analog digital converter (ADC) controller configured to generate the control signal in response to a gain adjust signal;
- and
- an analog digital converter (ADC) configured to adjust an analog gain in response to the control signal and amplify the analog signal using the analog gain, wherein the analog logic determines k based on a signal level of the analog signal and a level of the gain adjust signal,
- wherein the image sensor further comprises a digital logic configured to receive the second digital code and receive the control signal from the ADC controller, the digital logic including a random bit generator configured to generate k number of random bits based on the control signal, and
- wherein the digital logic is configured to combine the second digital code with the k number of random bits to generate a third digital code, the third digital code being represented by the same number of bits as the first digital code.
9 more elements
A method of operating an image sensing device, the method comprising:
- generating an analog signal corresponding to an electrical charge generated by at least one pixel in response to incident light;
- converting the analog signal from an output line of the at least one pixel to generate a first digital code consisting of N-bits, where N is a positive integer;
- receiving a control signal including a gain adjust signal for adjusting an analog gain of an analog digital converter (ADC);
- and
- eliminating k low-order bits of the first digital code in response to the control signal to generate a second digital code consisting of N-k bits, where k is an integer less than N and greater than zero and k is determined based on a signal level of the analog signal and a level of the gain adjust signal, wherein the N-k bits of the second digital code are the same as N-k high-order bits of the first digital code;
- generating k number of random bits based on the control signal;
- and
- outputting a third digital code by appending the k number of random bits to the second digital code such that the k number of random bits constitute lowest-order bits of the third digital code,
- wherein the third digital code is represented by the same number of bits as the first digital code.
6 more elements
An image sensor comprising:
- an image device that generates an analog signal in response to received light;
- an analog logic configured to:
- generate a first digital code consisting of N bits representing the analog signal, wherein N is a positive integer;
- receive a control signal;
- and
- generate a second digital code consisting of N-k bits by eliminating k low-order bits of the first digital code in response to the control signal including a gain adjust signal for adjusting an analog gain of an analog digital converter (ADC), wherein the N-k bits of the second digital code are the same as N-k high-order bits of the first digital code;
- and
- a digital logic configured to receive the second digital code and receive the control signal from the analog logic, the digital logic including a random bit generator configured to generate k number of random bits based on the control signal,
- wherein the digital logic is configured to combine the second digital code with the k number of random bits to generate a third digital code, the third digital code being represented by the same number of bits as the first digital code.
6 more elements
Dependencies are inferred from the claim text.