Layered semi parallel LDPC decoder system having single permutation network

A layered semi-parallel LDPC decoder system having a single permutation network, characterized by comprising a layered decoding architecture of the single permutation network, a layered semi-parallel decoding architecture of the single permutation network, a pipeline design for layered semi-parallel decoding and a hardware framework of a layered semi-parallel LDPC decoder;

• for the layered decoding architecture of the single permutation network, a permutation network is used for cyclic shift operation for layered decoding before and after check node processing, and the cyclic shift operation of the decoder can be completed only through the single permutation network by modifying the cyclic shift value of each information block transferred from a variable node to a check node;
• compared with a full-parallel architecture, a semi-parallel architecture only instantiates i APP RAM (a posteriori probability random access memory) modules and i VFU (variable-node function units), so the number of permutation network modules is also reduced to i;
• the degree of parallelism of a variable node processor is reduced from N to N/2, and the degree of parallelism of a check node processor is maintained to z, wherein
• i
• =
• N
• /
• z
• 2
• ,
• N is an information code length of an LDPC code, and z is an expansion factor;
• the hardware framework of a layered semi-parallel LDPC decoder comprises a top control module, an MUX2_1 module, a permutation network module, an APP RAM (a posteriori probability random access memory) module, a MUX3_1 module, a check-node function unit CFU module and a sequence output module;
• the top control module controls the time sequence of other modules through state transfer of control signals;
• the MUX2_1 module is a one-from-two module, which is used to select LLR (log-likelihood ratio) information first input for decoding and APPs (a posteriori probability) updated by the check node and connected with the APP RAM module;
• the APP RAM module stores a first half of APPs and a second half of APPs, and is respectively connected with the MUX2_1 module, the MUX3_1 module and the sequence output module;
• the MUX3_1 module is a one-from-three module, which is used to select LLR information first input for decoding, APPs updated by the check node and all-zero information in case that a check matrix is negative, one end of the MUX3_1 module is connected with the APP RAM module, and the other end is connected with the permutation network module;
• the permutation network module is used for cyclic shift operation of parallel data, one end of the permutation network module is in signal connection with the MUX3_1 module, and the other end is in signal connection with the APP RAM module;
• the check-node function unit CFU module is used to calculate a minimum value and a second minimum value in inputs to update external information and APPs, one end of the check-node function unit CFU module is connected with the permutation network module, and the other end is in signal connection with the MUX2_1 module;
• the sequence output module is used for decoding decision outputs, and connected with the APP RAM module.