Biased amplifier
AssigneeTexas Instruments Incorporated
InventorSudheer Prasad
Life of this patent
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Abstract
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
Claims20
An amplifier, comprising:
- a compensation circuit;
- a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to a first node, a gate terminal coupled to a second node, a drain terminal coupled to a fourth node, and a bulk connection coupled to the first node;
- a second PMOS having a source terminal coupled to the first node, a gate terminal coupled to a third node, a drain terminal coupled to the compensation circuit at a fifth node, and a bulk connection coupled to the first node;
- a first n-type MOSFET (NMOS) having a drain terminal coupled to the fourth node and a gate terminal coupled to a sixth node;
- and
- a second NMOS having a drain terminal coupled to a source terminal of the first NMOS, a gate terminal coupled to the fourth node, and a source terminal coupled to a seventh node.
A circuit comprising:
- an input configured to couple to a sensor;
- an output;
- a ground input;
- a first capacitor and a second capacitor coupled in series between the output and the ground input;
- a first transistor that includes a source, a drain, a gate, and a bulk, wherein the first capacitor is coupled between the output and the gate of the first transistor;
- a second transistor that includes a source, a drain, a gate, and a bulk, wherein the input is coupled to the gate of the second transistor;
- and
- a first resistor and a second resistor coupled in series between the source of the first transistor and the source of the second transistor.
A circuit comprising:
- a positive supply voltage input;
- a negative supply voltage input;
- a first bias voltage input;
- a second bias voltage input;
- a sensor input;
- an output;
- a first transistor and a second transistor coupled in series between the positive supply voltage input and the output, wherein the first transistor includes a gate coupled to the first bias voltage input and the second transistor includes a gate coupled to the second bias voltage input;
- a first capacitor and a second capacitor coupled in series between the output and the negative supply voltage input;
- a third transistor coupled between the output and the negative supply voltage input;
- a fourth transistor and a fifth transistor coupled in series between the positive supply voltage input and a first node, wherein the fourth transistor includes a gate coupled to the first bias voltage input and the fifth transistor includes a gate coupled to the second bias voltage input;
- a first resistor, a sixth transistor, a seventh transistor, and an eighth transistor coupled in series between the first node and the negative supply voltage input, wherein the fourth transistor includes a gate coupled to a second node between the first capacitor and the second capacitor;
- and
- a second resistor, a ninth transistor, a tenth transistor, and an eleventh transistor coupled in series between the first node and the negative supply voltage input, wherein the ninth transistor includes a gate coupled to the sensor input.
Dependencies are inferred from the claim text.