# US 12,218,253 B2 · Flash memory device with three dimensional half flash structure and methods for forming the same

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- Number: US 12,218,253 B2
- Document ID: US12218253B2
- Status: Granted
- Kind: B2
- Application number: 18/301,220
- Filed: 2023-04-15
- Published: 2023-08-10
- Granted: 2025-02-04
- Earliest claimed: 2021-03-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Yu-Chu Lin; Chi-Chung Jen; Wen-Chih Chiang; Yi-Ling Liu; Huai-Jen Tung; Keng-Ying Liao
- Web page: https://patentgrep.com/patent/US12218253B2

## CPC

- H10D 30/68: Floating-gate IGFETs
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10B 41/10: characterised by the top-view layout
- H10B 41/30: characterised by the memory core region
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

## Claims

### Claim 1

A memory cell, comprising:
a channel region in a substrate;
a gate structure comprising:
a control gate dielectric layer on the channel region and having a first length in a first direction;
a control gate on the control gate dielectric layer and having a second length in the first direction less than the first length; and
a second sidewall spacer on a second sidewall of the control gate and on the control gate dielectric layer;
a first contact contacting the control gate dielectric layer over the channel region, having a height greater than a height of the control gate and including an outermost sidewall opposite the control gate and over the channel region; and
an interlevel dielectric layer on opposing sides of the first contact and contacting the control gate dielectric layer at the second sidewall spacer and over the channel region.

### Claim 2 (depends on 1)

The memory cell of claim 1, further comprising:
a second contact contacting the control gate dielectric layer.

### Claim 3 (depends on 2)

The memory cell of claim 2, wherein the first contact is configured to program and erase the memory cell, and the second contact is configured to read the memory cell.

### Claim 4 (depends on 2)

The memory cell of claim 2, further comprising:
a third contact electrically connected to the control gate.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein the gate structure further comprises:
a tunnel dielectric layer on the channel region; and
a floating gate electrode on the tunnel dielectric layer, wherein the control gate dielectric layer is on the floating gate electrode.

### Claim 6 (depends on 5)

The memory cell of claim 5, wherein the first contact comprises an outermost sidewall located opposite the control gate and over the floating gate electrode.

### Claim 7 (depends on 5)

The memory cell of claim 5, wherein the control gate comprises:
a first sidewall substantially aligned with a first sidewall of the control gate dielectric layer and a first sidewall of the floating gate electrode; and
the second sidewall opposite the first sidewall of the control gate, and located on the control gate dielectric layer.

### Claim 8 (depends on 7)

The memory cell of claim 7, wherein the gate structure further comprises:
a first sidewall spacer on the first sidewall of the control gate, the first sidewall of the control gate dielectric layer and the first sidewall of the floating gate electrode; and
the second sidewall spacer on the second sidewall of the control gate, and located on the control gate dielectric layer.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein the first contact contacts the control gate dielectric layer adjacent to the second sidewall spacer.

### Claim 10 (depends on 5)

The memory cell of claim 5, wherein the control gate dielectric layer comprises:
a first oxide layer having a first thickness on the floating gate electrode;
a nitride layer on the first oxide layer; and
a second oxide layer having a second thickness greater than the first thickness on the nitride layer, wherein the first contact contacts a surface of the second oxide layer.

### Claim 11 (depends on 10)

The memory cell of claim 10, wherein the second thickness of the second oxide layer is in a range from 5% to 10% greater than the first thickness of the first oxide layer.

### Claim 12 (depends on 1)

The memory cell of claim 1, wherein the substrate further comprises a source region and a drain region, and the channel region extends in the first direction from the source region to the drain region.

### Claim 13 (depends on 12)

The memory cell of claim 12, wherein each of the source region and the drain region comprises an active extension region and a deep active region.

### Claim 14 (depends on 13)

The memory cell of claim 13, wherein the active extension region has a dopant concentration in a range from 2×1020 to 2×1021.

### Claim 15

A method of forming a memory cell, comprising:
forming a channel region in a substrate;
forming a control gate dielectric layer of a gate structure on the channel region, wherein the control gate dielectric layer has a first length in a first direction;
forming a control gate of the gate structure on the control gate dielectric layer, wherein the control gate has a second length in the first direction less than the first length;
forming a second sidewall spacer on a second sidewall of the control gate and on the control gate dielectric layer;
forming a first contact contacting the control gate dielectric layer over the channel region, having a height greater than a height of the control gate and including an outermost sidewall opposite the control gate and over the channel region; and
forming an interlevel dielectric layer on opposing sides of the first contact such that the interlevel dielectric layer contacts the control gate dielectric layer at the sidewall spacer and over the channel region.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a second contact contacting the control gate dielectric layer, wherein the first contact is configured to program and erase the memory cell, and the second contact is configured to read the memory cell.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
forming a source region and a drain region in the substrate, wherein the channel region extends in the first direction from the source region to the drain region;
forming a tunnel dielectric layer of the gate structure on the channel region; and
forming a floating gate electrode of the gate structure on the tunnel dielectric layer, wherein the forming of the control gate dielectric layer comprises forming the control gate dielectric layer on the floating gate electrode.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a first sidewall spacer on a first sidewall of the control gate, a first sidewall of the control gate dielectric layer and a first sidewall of the floating gate electrode, wherein the first contact contacts the control gate dielectric layer adjacent to the second sidewall spacer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the forming of the control gate dielectric layer comprises:
forming a first oxide layer having a first thickness on the floating gate electrode;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer having a second thickness greater than the first thickness on the nitride layer, wherein the first contact contacts a surface of the second oxide layer.

### Claim 20

A memory device comprising:
a plurality of memory cells arranged in a plurality of columns, wherein each memory cell of the plurality of memory cells comprises:
a channel region in a substrate;
a gate structure on the substrate, wherein the gate structure comprises:
a control gate dielectric layer on the channel region and having a first length in a first direction;
a control gate on the control gate dielectric layer and having a second length in the first direction less than the first length; and
a second sidewall spacer on a second sidewall of the control gate and on the control gate dielectric layer;
a first contact contacting the control gate dielectric layer over the channel region, having a height greater than a height of the control gate and including an outermost sidewall opposite the control gate and over the channel region; and
an interlevel dielectric layer on opposing sides of the first contact and contacting the control gate dielectric layer at the second sidewall spacer and over the channel region; and
a plurality of isolation regions alternatingly formed with the plurality of columns in the first direction.