# US 12,218,250 B2 · Oxide semiconductor transistor structure in 3-d device and methods for forming the same

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- Number: US 12,218,250 B2
- Document ID: US12218250B2
- Status: Granted
- Kind: B2
- Application number: 18/334,496
- Filed: 2023-06-14
- Published: 2023-10-12
- Granted: 2025-02-04
- Earliest claimed: 2020-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Kuo-Chang Chiang; Hung-Chang Sun; Sheng-Chih Lai; TsuChing Yang; Yu-Wei Jiang; Feng-Cheng Yang; Neil Quinn Murray
- Web page: https://patentgrep.com/patent/US12218250B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/2925: {Surface structures}
- H10P 14/3226: {Oxides}
- H10P 14/3234: {being oxide semiconducting materials (Group IIB-VIA semiconductors H10P14/3224)}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/3451: {Structure}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

## Claims

### Claim 1

A transistor comprising:
a gate electrode;
a dielectric layer;
source and drain electrodes; and
a channel layer comprising:
a first oxide semiconductor layer having a first oxygen concentration;
a second oxide semiconductor layer having a second oxygen concentration; and
a third oxide semiconductor layer having a third oxygen concentration, wherein the second oxide semiconductor layer is located between the first oxide semiconductor layer and the third oxide semiconductor layer; and
wherein the second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration, and
a thickness of the second oxide semiconductor layer is greater than a combined thickness of the first oxide semiconductor layer and the third oxide semiconductor layer.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the first oxygen concentration and the third oxygen concentration are equal.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the dielectric layer is located adjacent the first oxide semiconductor layer opposite the second oxide semiconductor layer, and the gate electrode is located adjacent the dielectric layer opposite the first oxide semiconductor layer.

### Claim 4 (depends on 3)

The transistor of claim 3, wherein the dielectric layer comprises a material selected from a group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), alumina (Al2O3), hafnium dioxide-alumina (HfO2—Al2O3), tantalum oxide (Ta2O5), SiOx/SiNy/SiOx or ferroelectrics.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein:
the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise InxGayZnzMO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof and 0<(x, y, z)<1; and
the source and drain electrodes comprise a conductive metal material.

### Claim 6 (depends on 5)

The transistor of claim 5, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise different compositions of InxGayZnzMw.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein a ratio of a carrier concentration in the second oxide semiconductor layer to the first oxide semiconductor layer is in a range of 1:1 to 1:109.

### Claim 8 (depends on 1)

The transistor of claim 1, wherein a ratio of the thickness of the second oxide semiconductor layer to the thickness of the first oxide semiconductor layer is in a range of 10:1 to 100:1 and a ratio of the thickness of the second oxide semiconductor layer to the thickness of the third oxide semiconductor layer is in a range of 10:1 to 100:1.

### Claim 9

A method of forming an oxide semiconductor transistor, comprising:
depositing a gate electrode;
depositing a dielectric layer;
depositing a channel layer, comprising:
depositing a first oxide semiconductor layer;
depositing a second oxide semiconductor layer;
depositing a third oxide semiconductor layer,
wherein an oxygen concentration of the second oxide semiconductor layer is lower than an oxygen concentration of the first oxide semiconductor layer, and
an oxygen concentration of the third oxide semiconductor layer, and
a thickness of the second oxide semiconductor layer is greater than a combined thickness of the first oxide semiconductor layer and third oxide semiconductor layer; and
forming a source electrode and a drain electrode in contact with the channel layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the channel layer is deposited using atomic layer deposition.

### Claim 11 (depends on 9)

The method of claim 9, wherein the channel layer is deposited using physical vapor deposition.

### Claim 12 (depends on 9)

The method of claim 9, wherein the composition of the first oxide semiconductor layer and the composition of the third oxide semiconductor layer are the same.

### Claim 13 (depends on 9)

The method of claim 9, wherein a carrier concentration of the second oxide semiconductor layer is greater than a combined carrier concentration of the first oxide semiconductor layer and the third oxide semiconductor layer.

### Claim 14

A method of forming an oxide semiconductor transistor, comprising:
depositing a gate electrode;
depositing a dielectric layer;
depositing a channel layer, comprising:
depositing a first oxide semiconductor layer having a first oxygen concentration;
depositing a second oxide semiconductor layer having a second oxygen concentration;
subjecting the second oxide semiconductor layer to a thermal treatment at an elevated temperature in an environment that is essentially free of oxygen gas (O2);
depositing a third oxide semiconductor layer having a third oxygen concentration;
wherein the second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration; and
forming a source electrode and a drain electrode in contact with the channel layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are formed using a physical vapor deposition process.

### Claim 16 (depends on 15)

The method of claim 15, wherein a flow rate ratio of O2/(Ar+O2) during the deposition of the second oxide semiconductor layer is greater than or equal to 0 and less than or equal to 0.05.

### Claim 17 (depends on 14)

The method of claim 14, further comprising annealing the channel layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the thermal treatment of the second oxide semiconductor layer is conducted in the presence of a reduction gas to promote desorption of oxygen from the second oxide semiconductor layer, and the channel layer is annealed in the presence of an oxygen-containing gas to promote oxidation of the third oxide semiconductor layer.

### Claim 19 (depends on 14)

The method of claim 14, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprise compositions of InxGayZnzMO, wherein M is selected from the group consisting of Ti, Al, Ag, Si, Sn and combinations thereof.

### Claim 20 (depends on 19)

The method of claim 19, wherein a ratio of In:Ga:Zn:M is identical in each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer.