# US 12,218,249 B2 · Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal

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- Number: US 12,218,249 B2
- Document ID: US12218249B2
- Status: Granted
- Kind: B2
- Application number: 18/227,361
- Filed: 2023-07-28
- Published: 2023-11-16
- Granted: 2025-02-04
- Earliest claimed: 2009-12-04
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US12218249B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/40: Crystalline structures
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/80: characterised by the materials
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

## Claims

### Claim 1

A semiconductor device comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
an oxide semiconductor layer including a channel formation region of a transistor, over the first insulating layer; and
a second conductive layer in contact with a top surface of the oxide semiconductor layer,
wherein the first conductive layer is configured to be a gate electrode of the transistor,
wherein the second conductive layer is configured to be a source electrode or a drain electrode of the transistor,
wherein the oxide semiconductor layer includes a first region overlapping the first conductive layer, a second region overlapping the first conductive layer and the second conductive layer, and a third region overlapping the second conductive layer,
wherein the first region includes a crystal grain whose c-axis is aligned, and
wherein the second region is closer to the first conductive layer than the first region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a third conductive layer over the oxide semiconductor layer and the second conductive layer.