# US 12,218,246 B2 · Semiconductor device and method for manufacturing semiconductor device

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- Number: US 12,218,246 B2
- Document ID: US12218246B2
- Status: Granted
- Kind: B2
- Application number: 17/414,490
- Filed: 2019-11-19
- Published: 2022-03-10
- Granted: 2025-02-04
- Earliest claimed: 2018-12-28
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Shinya Sasagawa; Katsuaki Tochibayashi; Tsutomu Murakawa; Erika Takahashi
- Web page: https://patentgrep.com/patent/US12218246B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.

## Claims

### Claim 1

A semiconductor device comprising a transistor,
wherein the transistor comprises:
a first insulator;
a first oxide over the first insulator;
a first conductor, a second conductor, and a second oxide over the first oxide, the second oxide being between the first conductor and the second conductor;
a second insulator over the second oxide; and
a third conductor over the second insulator,
wherein a top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor,
wherein the first oxide in the region overlapping with the third conductor comprises a curved surface between a side surface and the top surface of the first oxide, and
wherein a curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein, in a channel length direction, a difference between a level of the top surface of the first oxide in the region overlapping with the third conductor and a level of the top surface of the first oxide in the region overlapping with the first conductor is greater than or equal to 1 nm and less than or equal to 5 nm, with respect to a bottom surface of the first insulator.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein in a channel width direction of the transistor, a half of a difference between a length of a bottom surface of the first oxide in the region overlapping with the first conductor and a length of a bottom surface of the first oxide in the region overlapping with the third conductor is greater than or equal to 2 nm and less than or equal to 10 nm.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the transistor comprises a third oxide and a fourth oxide,
wherein the third oxide is between the first oxide and the first conductor,
wherein the fourth oxide is between the first oxide and the second oxide, and
wherein in a channel length direction of the transistor, a bottom surface of the second oxide is at a lower position than a position of a bottom surface of the third oxide and a position of a bottom surface of the fourth oxide.

### Claim 5

A semiconductor device comprising a plurality of transistors, wherein the plurality of transistors each comprise:
a first insulator;
a first oxide over the first insulator;
a first conductor, a second conductor, and a second oxide over the first oxide, the second oxide being between the first conductor and the second conductor;
a second insulator over the second oxide; and
a third conductor over the second insulator,
wherein a top surface the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor,
wherein the first oxide in the region overlapping with the third conductor comprises a curved surface between a side surface and the top surface of the first oxide, and
wherein in Id-Vg characteristics of the plurality of transistors, a standard deviation σ of Vsh is less than 60 mV.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5,
wherein a channel length of each of the plurality of transistors is greater than or equal to 40 nm and less than or equal to 80 nm, and
wherein a channel width of each of the plurality of transistors is greater than or equal to 40 nm and less than or equal to 80 nm.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein a curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.

### Claim 8

A semiconductor device comprising a transistor,
wherein the transistor comprises:
a first insulator;
a first oxide over the first insulator;
a first conductor, a second conductor, and a second oxide over the first oxide, the second oxide being between the first conductor and the second conductor;
a second insulator over the second oxide;
a third conductor over the second insulator; and
a third insulator in contact with a top surface of the first conductor, a top surface of the second conductor, and a part of a side surface of the first oxide,
wherein in a channel width of the transistor, a length of a bottom surface of the first oxide in a region overlapping with the first conductor is larger than a length of a bottom surface of the first oxide in a region overlapping with the third conductor,
wherein the first oxide in the region overlapping with the third conductor comprises a curved surface between the side surface and a top surface of the first oxide,
wherein the first oxide comprises indium, an element M, and zinc,
wherein the element M is any one of gallium, yttrium, and tin,
wherein the third insulator comprises an element that is to be an impurity of the first oxide, and
wherein a concentration ratio of the element to the element M at the side surface of the first oxide in the region overlapping with the third conductor is lower than a concentration ratio of the element to the element M at the side surface of the first oxide in a region overlapping with the first conductor.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the element in the third insulator is aluminum.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein a curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.