# US 12,218,241 B2 · Semiconductor device structure with etch stop layer for reducing RC delay

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- Number: US 12,218,241 B2
- Document ID: US12218241B2
- Status: Granted
- Kind: B2
- Application number: 17/705,885
- Filed: 2022-03-28
- Published: 2022-07-14
- Granted: 2025-02-04
- Earliest claimed: 2017-07-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chung-Ting Ko; Bo-Cyuan Lu; Jr-Hung Li; Chi-On Chui
- Web page: https://patentgrep.com/patent/US12218241B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/40: Crystalline structures
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/6316: {Formation by nitridation, e.g. nitridation of the substrate}
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a spacer element covering a first sidewall of the gate structure. The semiconductor device structure further includes a source/drain portion in the substrate, and the spacer element is between the source/drain portion and the gate structure. In addition, the semiconductor device structure includes an etch stop layer covering the source/drain portion. The etch stop layer includes a first nitride layer covering the source/drain portion and having a second sidewall, and the second sidewall is in direct contact with the spacer element. The etch stop layer also includes a first silicon layer covering the first nitride layer and having a third sidewall, and the third sidewall is in direct contact with the spacer element.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate;
a gate structure over the substrate;
a spacer element covering a first sidewall of the gate structure;
a source/drain portion in the substrate, wherein the spacer element is between the source/drain portion and the gate structure;
an etch stop layer covering the source/drain portion, wherein a topmost surface of the etch stop layer is closer to the substrate than a topmost surface of the gate structure, and the etch stop layer comprises:
a first nitride layer covering the source/drain portion and having a second sidewall, wherein the second sidewall is in direct contact with the spacer element; and
a first silicon layer covering the first nitride layer and having a third sidewall, wherein the third sidewall is in direct contact with the spacer element; and
a dielectric layer over the etch stop layer, wherein the dielectric layer has a fourth sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the fourth sidewall.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the second sidewall and the third sidewall are substantially level with each other.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the first silicon layer is in direct contact with the first nitride layer.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the spacer element separates the gate structure from the etch stop layer.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the etch stop layer further comprises:
a second nitride layer covering the first silicon layer.

### Claim 6 (depends on 5)

The semiconductor device structure as claimed in claim 5, wherein the second nitride layer has a fourth sidewall, and the fourth sidewall is in direct contact with the spacer element.

### Claim 7 (depends on 6)

The semiconductor device structure as claimed in claim 6, wherein the etch stop layer further comprises:
a second silicon layer covering the second nitride layer.

### Claim 8 (depends on 7)

The semiconductor device structure as claimed in claim 7, wherein the second silicon layer has a fifth sidewall, and the fifth sidewall is in direct contact with the spacer element.

### Claim 9 (depends on 8)

The semiconductor device structure as claimed in claim 8, wherein the second sidewall, the third sidewall, the fourth sidewall, and the fifth sidewall are aligned with each other.

### Claim 10

A semiconductor device structure, comprising:
a substrate;
a gate structure over the substrate;
a spacer element covering a first sidewall of the gate structure;
a source/drain portion in the substrate, wherein the spacer element separates the source/drain portion from the gate structure;
a nitride layer over the source/drain portion and having a second sidewall, wherein the second sidewall faces the spacer element;
a silicon layer over the nitride layer and having a third sidewall, wherein a topmost surface of the silicon layer is closer to the source/drain portion than a topmost surface of the spacer element, the third sidewall faces the spacer element, and the second sidewall is under and connected to the third sidewall; and
a dielectric layer over the silicon layer, wherein the dielectric layer has a fourth sidewall and a bottom surface, the silicon layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the fourth sidewall, the second sidewall, and the third sidewall.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein
the second sidewall of the nitride layer, the third sidewall of the silicon layer, and the fourth sidewall are aligned with each other.

### Claim 12 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the nitride layer is in direct contact with the source/drain portion.

### Claim 13 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the nitride layer is a first flat layer, and the silicon layer is a second flat layer.

### Claim 14 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the topmost surface of the spacer element, a topmost surface of the dielectric layer, and a topmost surface of the gate structure are substantially level with each other.

### Claim 15

A semiconductor device structure, comprising:
a substrate;
a gate structure over the substrate;
a spacer element covering a first sidewall of the gate structure;
a nitride layer over the substrate and having a second sidewall;
a silicon layer over the nitride layer and having a third sidewall, wherein a topmost surface of the silicon layer is lower than a topmost surface of the gate structure; and
a dielectric layer over the silicon layer and having a fourth sidewall and a bottom surface, wherein the silicon layer is in direct contact with the bottom surface, and the second sidewall, the third sidewall, and the fourth sidewall are in direct contact with the spacer element.

### Claim 16 (depends on 15)

The semiconductor device structure as claimed in claim 15, wherein the second sidewall is aligned with the third sidewall.

### Claim 17 (depends on 15)

The semiconductor device structure as claimed in claim 15, wherein the second sidewall is connected to the third sidewall.

### Claim 18 (depends on 15)

The semiconductor device structure as claimed in claim 15, further comprising:
a source/drain portion in the substrate and under the nitride layer.

### Claim 19 (depends on 18)

The semiconductor device structure as claimed in claim 18, wherein a first crystallinity of the source/drain portion is greater than a second crystallinity of the spacer element.

### Claim 20 (depends on 15)

The semiconductor device structure as claimed in claim 15, wherein a topmost surface of the spacer element, a topmost surface of the dielectric layer, and the topmost surface of the gate structure are substantially level with each other.