# US 12,218,237 B2 · Semiconductor device, and method for manufacturing semiconductor device

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- Number: US 12,218,237 B2
- Document ID: US12218237B2
- Status: Granted
- Kind: B2
- Application number: 17/276,248
- Filed: 2019-09-11
- Published: 2022-01-27
- Granted: 2025-02-04
- Earliest claimed: 2018-09-28
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Semiconductor Solutions Corporation
- Inventors: Yuki Yanagisawa; Takashi Futatsuki
- Web page: https://patentgrep.com/patent/US12218237B2

## CPC

- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/01312: {the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode layer that is provided on the gate insulating film and contains impurity ions; and source or drain regions that are provided on the semiconductor substrate on both sides of the gate electrode layer and contain conductive impurities, in which a concentration of the impurity ions in the gate electrode layer is higher than concentrations of the conductive impurities in the source or drain regions.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate in which a support substrate, an insulating film, and a semiconductor layer are laminated;
a gate insulating film provided on the semiconductor substrate;
a sidewall insulating film;
a gate electrode layer that is provided on the gate insulating film and contains impurity ions, wherein the gate electrode layer is formed in a multilayer structure, wherein at least one layer of the multilayer structure is formed of a polysilicon layer including phosphorus ions, and wherein the polysilicon layer is formed closest to the semiconductor layer; and
source or drain regions that are provided in the semiconductor substrate on both sides of the gate electrode layer and contain conductive impurities, wherein a concentration of the impurity ions in the gate electrode layer is higher than a concentration of the conductive impurities in the source or drain regions.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a concentration of the impurity ions in the polysilicon layer is 6.0×1020/cm3 or more.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive impurities are n-type impurities.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode layer is formed of polysilicon.

### Claim 5

A method for manufacturing a semiconductor device comprising:
forming a gate insulating film uniformly on a semiconductor substrate in which a support substrate, an insulating film, and a semiconductor layer are laminated;
forming a sidewall insulating film;
forming a gate electrode layer uniformly on the gate insulating film, wherein the gate electrode layer is formed in a multilayer structure, wherein at least one layer of the multilayer structure is formed of a polysilicon layer including phosphorus ions, and wherein the polysilicon layer is formed closest to the semiconductor layer;
introducing impurity ions into the gate electrode layer;
patterning the gate insulating film and the gate electrode layer; and
introducing conductive impurities into the semiconductor substrate on both sides of the gate insulating film and the gate electrode layer to form source or drain regions in the semiconductor substrate, wherein a concentration of the impurity ions introduced into the gate electrode layer is higher than a concentration of the conductive impurities introduced into the source or drain regions.