# US 12,218,224 B2 · Method for forming semiconductor device

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- Number: US 12,218,224 B2
- Document ID: US12218224B2
- Status: Granted
- Kind: B2
- Application number: 17/885,058
- Filed: 2022-08-10
- Published: 2022-12-01
- Granted: 2025-02-04
- Earliest claimed: 2021-01-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wang-Chun Huang; Hou-Yu Chen; Kuan-Lun Cheng; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12218224B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

## Claims

### Claim 1

A method, comprising:
receiving a workpiece comprising:
a first active region and a second active region,
an isolation feature disposed between lower portions of the first active region and the second active region,
a dielectric fin disposed on the isolation feature and between the first active region and the second active region;
depositing a gate dielectric layer over the first active region, the isolation feature, the dielectric fin, and the second active region;
depositing a protection layer over the gate dielectric layer;
depositing a cap layer over the protection layer;
selectively removing the cap layer over the first active region while the second active region remains covered by the cap layer;
forming a first metal layer over the first active region, the dielectric fin and the cap layer over the second active region;
selectively removing the first metal layer and the cap layer over the second active region; and
forming a second metal layer over the second active region and the first metal layer over the first active region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the dielectric fin comprises silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, silicon oxide, silicon oxynitride, or silicon oxycarbonitride.

### Claim 3 (depends on 1)

The method of claim 1, wherein the protection layer comprises a metal nitride.

### Claim 4 (depends on 3)

The method of claim 3, wherein the protection layer comprises titanium nitride (TiN), tantalum nitride (TaN), or titanium silicon nitride (TiSiN).

### Claim 5 (depends on 1)

The method of claim 1, wherein the cap layer comprises silicon (Si).

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
etching back the cap layer until the cap layer no longer merges over the dielectric fin.

### Claim 7 (depends on 1)

The method of claim 1, wherein the selectively removing comprises:
depositing a hard mask layer over the workpiece;
depositing a bottom antireflective coating (BARC) layer over the hard mask layer;
patterning the BARC layer and the hard mask layer to form a mask film; and
etching the workpiece using the mask film as an etch mask to remove the cap layer over the first active region.

### Claim 8 (depends on 7)

The method of claim 7, wherein the hard mask layer comprises aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), zirconium oxide (ZrO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), hafnium oxide (HfO), zinc oxide (ZnO), yittrium oxide (YO), or titanium oxide (TiO).

### Claim 9

A method, comprising:
receiving a workpiece comprising:
a first stack of nanostructures and a second stack of nanostructures,
a dielectric fin disposed between the first stack of nanostructures and the second stack of nanostructures;
depositing a protection layer over the first stack of nanostructures, the dielectric fin, and the second stack of nanostructures;
depositing a cap layer over the protection layer;
selectively removing the cap layer over the first stack of nanostructures while the second stack of nanostructures remain covered by the cap layer;
forming a first metal layer over the first stack of nanostructures, the dielectric fin and the cap layer over the second stack of nanostructures;
selectively removing the first metal layer and the cap layer over the second stack of nanostructures; and
forming a second metal layer over the second stack of nanostructures and the first metal layer over the first stack of nano structures.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
before the depositing of the protection layer, depositing a gate dielectric layer over the first stack of nanostructures, the dielectric fin, and the second stack of nanostructures,
wherein the gate dielectric layer wraps around each of the first stack of nanostructures and each of the second stack of nanostructures.

### Claim 11 (depends on 9)

The method of claim 9, wherein the protection layer wraps around each of the first stack of nanostructures and each of the second stack of nanostructures.

### Claim 12 (depends on 9)

The method of claim 9, wherein the protection layer comprises titanium nitride (TiN), tantalum nitride (TaN), or titanium silicon nitride (TiSiN).

### Claim 13 (depends on 9)

The method of claim 9, wherein the selectively removing comprises:
depositing a hard mask layer over the workpiece;
depositing a bottom antireflective coating (BARC) layer over the hard mask layer;
patterning the BARC layer and the hard mask layer to form a mask film; and
etching the workpiece using the mask film as an etch mask to remove the cap layer over the first stack of nanostructures.

### Claim 14 (depends on 13)

The method of claim 13, wherein the hard mask layer comprises aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), zirconium oxide (ZrO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), hafnium oxide (HfO), zinc oxide (ZnO), yittrium oxide (YO), or titanium oxide (TiO).

### Claim 15

A method, comprising:
receiving a workpiece comprising:
a first active region and a second active region, and
a dielectric fin disposed between the first active region and the second active region;
forming a gate dielectric layer over the first active region, the dielectric fin and the second active region;
after the forming of the gate dielectric layer, depositing a cap layer over the dielectric fin, the first active region and the second active region;
etching back the cap layer until the dielectric fin separates the cap layer into a first portion over the first active region and a second portion over the second active region;
after the etching back, selectively removing the first portion of the cap layer over the first active region;
forming a first metal layer over the first active region, the dielectric fin and the cap layer over the second active region;
selectively removing the first metal layer and the cap layer over the second active region; and
forming a second metal layer over the second active region and the first metal layer over the first active region.

### Claim 16 (depends on 15)

The method of claim 15, wherein the cap layer comprises silicon.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
before the depositing of the cap layer, depositing a protection layer over the first active region, the second active region, and the dielectric fin.

### Claim 18 (depends on 17)

The method of claim 17, wherein the protection layer comprises titanium nitride.

### Claim 19 (depends on 15)

The method of claim 15, wherein, after the selectively removing of the first metal layer and the cap layer over the second active region, a portion of the first metal layer remains disposed over a top surface of the dielectric fin.

### Claim 20 (depends on 15)

The method of claim 15, wherein, after the forming of the second metal layer over the second active region, a top surface of the dielectric fin is spaced apart from the second metal layer by the first metal layer.