# US 12,218,219 B2 · Spacer structure for semiconductor device

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- Number: US 12,218,219 B2
- Document ID: US12218219B2
- Status: Granted
- Kind: B2
- Application number: 17/459,788
- Filed: 2021-08-27
- Published: 2023-03-02
- Granted: 2025-02-04
- Earliest claimed: 2021-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jung-Hao Chang; Fo-Ju Lin; Fang-Wei Lee; Li-Te Lin; Pinyen Lin
- Web page: https://patentgrep.com/patent/US12218219B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

## Claims

### Claim 1

A method, comprising:
forming a fin structure over a substrate, wherein the fin structure comprises first and second sacrificial layers;
forming a recess structure in a first portion of the fin structure;
selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure; and
forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

### Claim 2 (depends on 1)

The method of claim 1, wherein selectively etching the first sacrificial layer over the second sacrificial layer comprises performing a radical etching process to selectively etch the first sacrificial layer over the second sacrificial layer with an etching selectivity from about 10 to about 100.

### Claim 3 (depends on 1)

The method of claim 1, wherein selectively etching the first sacrificial layer over the second sacrificial layer comprises performing a hydrogen-free radical etching process to selectively etch the first sacrificial layer exposed by the recess structure over the second sacrificial layer exposed by the recess structure.

### Claim 4 (depends on 3)

The method of claim 3, wherein performing the hydrogen-free radical etching process comprises flowing a fluorine-containing processing gas.

### Claim 5 (depends on 1)

The method of claim 1, wherein selectively etching the first sacrificial layer over the second sacrificial layer comprises performing an etching process at a temperature from about-90° C. to about 15° C. to selectively etch the first sacrificial layer exposed by the recess structure over the second sacrificial layer exposed by the recess structure.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the fin structure comprises forming the first sacrificial layer with a first germanium concentration and forming the second sacrificial layer with a second germanium concentration less than the first germanium concentration.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the inner spacer layer comprises:
forming a dielectric layer over first and second side surfaces of the first and second sacrificial layers, respectively; and
etching the dielectric layer to expose the second side surface with the first side surface masked by the dielectric layer.

### Claim 8

A method, comprising:
forming first and second sacrificial layers over a substrate;
forming a recess structure to expose the first and second sacrificial layers;
selectively etching the exposed first sacrificial layer over the exposed second sacrificial layer; and
forming an inner spacer layer to cap the etched first sacrificial layer over the exposed second sacrificial layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein selectively etching the exposed first sacrificial layer over the exposed second sacrificial layer comprises performing a radical etching process to selectively etch the first sacrificial layer over the second sacrificial layer with an etching selectivity from about 10 to about 100.

### Claim 10 (depends on 8)

The method of claim 8, wherein selectively etching the exposed first sacrificial layer over the second exposed sacrificial layer comprises performing a hydrogen-free radical etching process to selectively etch the first sacrificial layer over the second sacrificial layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein performing the hydrogen-free radical etching process comprises flowing a fluorine-containing processing gas.

### Claim 12 (depends on 8)

The method of claim 8, wherein selectively etching the exposed first sacrificial layer over the second exposed sacrificial layer comprises performing an etching process at a temperature from about −90° C. to about 15° C. to selectively etch the first sacrificial layer over the second sacrificial layer.

### Claim 13 (depends on 8)

The method of claim 8, wherein forming the first and second sacrificial layers comprises forming the first sacrificial layer with a first germanium concentration and forming the second sacrificial layer with a second germanium concentration less than the first germanium concentration.

### Claim 14 (depends on 8)

The method of claim 8, wherein forming the inner spacer layer comprises:
forming a dielectric layer over first and second side surfaces of the first and second sacrificial layers, respectively; and
etching the dielectric layer to expose the second side surface with the first side surface masked by the dielectric layer.

### Claim 15

A method, comprising:
forming a first sacrificial layer on a substrate;
forming a stack of nanostructured layers and second sacrificial layers in an alternating configuration on the first sacrificial layer;
forming a polysilicon structure on the stack of nanostructured layers and second sacrificial layers;
forming an opening extending through the stack of nanostructured layers and second sacrificial layers and through the first sacrificial layer;
replacing the first sacrificial layer entirely with a dielectric layer;
forming a source/drain region in the opening; and
replacing the polysilicon structure and the second sacrificial layers with a gate structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first sacrificial layer comprises epitaxially growing a silicon germanium layer on the substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein replacing the first sacrificial layer comprises etching the first sacrificial layer to form a cavity between the substrate and the stack of nanostructured layers and second sacrificial layers.

### Claim 18 (depends on 17)

The method of claim 17, wherein replacing the first sacrificial layer further comprises depositing the dielectric layer to fill the cavity.

### Claim 19 (depends on 15)

The method of claim 15, further comprising etching the second sacrificial layers through the opening prior to replacing the first sacrificial layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising forming inner spacers along sidewalls of the second sacrificial layers prior to replacing the first sacrificial layer.