# US 12,218,218 B2 · Nanostructures formed over a substrate and a gate structure wrapping around the nanostructures

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- Number: US 12,218,218 B2
- Document ID: US12218218B2
- Status: Granted
- Kind: B2
- Application number: 17/690,354
- Filed: 2022-03-09
- Published: 2023-09-14
- Granted: 2025-02-04
- Earliest claimed: 2022-03-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yi-Ruei Jhan; Kuo-Cheng Chiang; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12218218B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion directly below the gate spacer layer and a second portion directly below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

## Claims

### Claim 1

A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a hard mask layer over the first fin structure and the second fin structure;
patterning the hard mask layer to form a trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer;
removing a portion of the first fin structure and a portion of the second fin structure to form a first S/D recess and a second S/D recess; and
forming a first source/drain (S/D) structure in the first S/D recess and a second S/D structure in the second S/D recess.

### Claim 2 (depends on 1)

The method for forming the semiconductor device structure as claimed in claim 1, further comprising:
forming a first oxide layer over the first fin structure and the second fin structure before forming the hard mask layer;
forming the hard mask layer over the first oxide layer;
forming the gate spacer layer in the trench;
removing a portion of the gate spacer layer and a portion of the first oxide layer exposed by the trench; and
removing a portion of a topmost first semiconductor layer to form a recess.

### Claim 3 (depends on 2)

The method for forming the semiconductor device structure as claimed in claim 2, further comprising:
forming a second oxide layer over the hard mask layer, wherein the hard mask layer is between the first oxide layer and the second oxide layer.

### Claim 4 (depends on 2)

The method for forming the semiconductor device structure as claimed in claim 2, further comprising:
forming a dummy gate dielectric layer in the recess, wherein the dummy gate dielectric layer is in direct contact with the topmost first semiconductor layer.

### Claim 5 (depends on 4)

The method for forming the semiconductor device structure as claimed in claim 4, further comprising:
removing the dummy gate electrode layer;
removing the dummy gate dielectric layer to form a trench;
removing the second semiconductor layers to form a gap; and
forming a gate structure in the trench and the gap.

### Claim 6 (depends on 1)

The method for forming the semiconductor device structure as claimed in claim 1, further comprising:
forming a dielectric feature between the first fin structure and the second fin structure, wherein the dielectric feature comprises a cap layer above the first fin structure, and the hard mask layer is over the cap layer.

### Claim 7 (depends on 6)

The method for forming the semiconductor device structure as claimed in claim 6, further comprising:
forming a first oxide layer over the cap layer;
forming the hard mask layer over the first oxide layer; and
removing the first oxide layer before forming the first S/D recess and the second S/D recess.

### Claim 8

A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a dielectric feature between the first fin structure and the second fin structure;
forming a hard mask layer over the first fin structure and the second fin structure;
patterning the hard mask layer to form a trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer;
removing the dummy gate electrode layer to form trench;
removing the second semiconductor layers to form a gap; and
forming a gate structure in the trench and the gap.

### Claim 9 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, further comprising:
removing a portion of the first semiconductor layers to form notches; and
forming inner spacer layers in the notches.

### Claim 10 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, further comprising:
forming a dielectric layer on the dielectric feature and the gate structure; and
forming a gate contact structure through the dielectric layer, wherein the gate contact structure is electrically connected to the gate structure.

### Claim 11 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, further comprising:
forming a cladding layer on the first fin structure and the second fin structure before forming the dielectric feature.

### Claim 12 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, further comprising:
removing a portion of a topmost first semiconductor layer to form a recess; and
forming a dummy gate dielectric layer in the recess.

### Claim 13 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, wherein the dielectric feature comprises a cap layer, wherein a top surface of the cap layer is higher than a top surface of the gate structure.

### Claim 14 (depends on 8)

The method for forming the semiconductor device structure as claimed in claim 8, further comprising:
forming a first oxide layer over the first fin structure and the second fin structure before forming the hard mask layer over the first fin structure and the second fin structure.

### Claim 15

A method for forming a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction;
forming a first oxide layer over the first fin structure and the second fin structure;
forming a hard mask layer on the first oxide layer;
patterning the hard mask layer to form a trench;
removing a portion of the first oxide layer exposed by the trench;
forming a gate spacer layer in the trench;
forming a dummy gate electrode layer in the trench and on the gate spacer layer;
removing the hard mask layer; and
replacing the dummy gate electrode layer with a gate structure.

### Claim 16 (depends on 15)

The method for forming the semiconductor device structure as claimed in claim 15, further comprising:
removing a portion of a topmost first semiconductor layer to form a recess; and
forming a dummy gate dielectric layer in the recess.

### Claim 17 (depends on 15)

The method for forming the semiconductor device structure as claimed in claim 15, further comprising:
forming a cladding layer on the first fin structure and the second fin structure; and
removing the cladding layer before replacing the dummy gate electrode layer with the gate structure.

### Claim 18 (depends on 15)

The method for forming the semiconductor device structure as claimed in claim 15, further comprising:
forming a dielectric feature between the first fin structure and the second fin structure, wherein the dielectric features comprises a liner layer, a filling layer and a cap layer on the liner layer and the filling layer.

### Claim 19 (depends on 18)

The method for forming the semiconductor device structure as claimed in claim 18, further comprising:
forming the hard mask layer on the dielectric feature.

### Claim 20 (depends on 15)

The method for forming the semiconductor device structure as claimed in claim 15, further comprising:
removing the second semiconductor layers to form nanostructures; and
forming the gate structure surrounding the nanostructures.