# US 12,218,217 B2 · Layer structure including dielectric layer, methods of manufacturing the layer structure, and electronic device including the layer structure

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- Number: US 12,218,217 B2
- Document ID: US12218217B2
- Status: Granted
- Kind: B2
- Application number: 17/545,442
- Filed: 2021-12-08
- Published: 2023-01-12
- Granted: 2025-02-04
- Earliest claimed: 2021-07-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yunseong Lee; Jinseong Heo; Taehwan Moon; Seunggeol Nam; Dukhyun Choe
- Web page: https://patentgrep.com/patent/US12218217B2

## CPC

- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10D 64/689: {having ferroelectric layers}
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an anti-ferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.

## Claims

### Claim 1

A layer structure comprising:
a lower layer;
an upper layer; and
a dielectric layer between the lower layer and the upper layer, the dielectric layer comprising
a first layer,
a second layer on the first layer, the second layer including an oxide layer, and
a third layer on the second layer,
wherein one of the first layer or the third layer is a ferroelectric and a remainder of the first and third layers is an anti-ferroelectric,
wherein the oxide layer directly contacts the ferroelectric and the anti-ferroelectric, and
wherein each of the first layer and the third layer is a single layer.

### Claim 2 (depends on 1)

The layer structure of claim 1, wherein the dielectric layer further includes a fourth layer on the third layer.

### Claim 3 (depends on 1)

The layer structure of claim 1, wherein a thickness of the second layer is less than or equal to 10% of a total thickness of the dielectric layer.

### Claim 4 (depends on 1)

The layer structure of claim 1, wherein the oxide layer includes an oxide having a band gap of 4 eV or more.

### Claim 5 (depends on 4)

The layer structure of claim 4, wherein an oxygen ratio of the oxide is less than or equal to an oxygen ratio of HfO2.

### Claim 6 (depends on 1)

The layer structure of claim 1, wherein at least one of the first layer or the third layer has a thickness less than or equal to 50% of a total thickness of the dielectric layer.

### Claim 7 (depends on 1)

The layer structure of claim 1, wherein each of the first layer and the third layer has a thickness 10% or more of a total thickness of the dielectric layer.

### Claim 8 (depends on 1)

The layer structure of claim 1, wherein at least one of the lower layer and the upper layer includes at least one of a semiconductor layer, a metal layer, or a two-dimensional material layer.

### Claim 9 (depends on 8)

The layer structure of claim 8, wherein the semiconductor layer includes at least one of a Si layer, a Ge layer, an oxide semiconductor layer, or a Group III-V compound semiconductor layer.

### Claim 10 (depends on 8)

The layer structure of claim 8, wherein the two-dimensional material layer includes at least one of a transition metal dichalcogenide layer, a quantum dot layer, or a carbon-based material layer.

### Claim 11 (depends on 1)

The layer structure of claim 1, wherein the third layer is the ferroelectric and includes at least one of an HfO-based ferroelectric layer, a ZrO layer, or a perovskite layer.

### Claim 12 (depends on 11)

The layer structure of claim 11, wherein the HfO-based ferroelectric layer includes at least one of an HfO2 layer or a HfO layer doped with a dopant.

### Claim 13 (depends on 12)

The layer structure of claim 12, wherein the dopant includes at least one of Si, Zr, Al, La, Y, Sr, Gd, or Mg.

### Claim 14 (depends on 2)

The layer structure of claim 2, wherein the first layer and the fourth layer each include an HfO2 layer.

### Claim 15 (depends on 1)

The layer structure of claim 1, wherein the oxide layer includes at least one of YO, LaO, MgO, SrO, BaO, or SiO.

### Claim 16

A method of manufacturing a dielectric layer, the method comprising:
forming a first layer on a substrate;
forming a second layer on the first layer, the second layer including an oxide; and
forming a third layer on the second layer,
wherein one of the first layer or the third layer is a ferroelectric, and a remainder of the first and third layers is an anti-ferroelectric wherein the oxide layer directly contacts the ferroelectric and the anti-ferroelectric, and wherein each of the first layer and the third layer is a single layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming a fourth layer on the third layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein a thickness of the second layer is 10% or less than a total thickness of the dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein the oxide has a band gap of 4 eV or more.

### Claim 20 (depends on 16)

The method of claim 16, wherein the second layer includes at least one of YO, LaO, MgO, SrO, BaO or SiO.

### Claim 21 (depends on 16)

The method of claim 16, wherein the substrate includes at least one of a metal layer, a Si layer, a Ge layer, an oxide semiconductor layer, a Group III-V compound semiconductor layer, a two-dimensional material layer, a transition metal dichalcogenide layer, a quantum dot layer, or a carbon-based material layer.

### Claim 22 (depends on 16)

The method of claim 16, wherein the third layer is the ferroelectric and includes at least one of an HfO2 layer, a ZrO layer, an HfO layer doped with a dopant, or a perovskite layer.

### Claim 23 (depends on 22)

The method of claim 22, wherein the dopant includes at least one of Si, Zr, Al, La, Y, Sr, Gd, or Mg.

### Claim 24 (depends on 17)

The method of claim 17, wherein the second layer is formed between the third layer and the fourth layer.

### Claim 25 (depends on 1)

A transistor comprising:
a first doped region;
a second doped region separated from the first doped region; and
a gate stack between the first and second doped regions, the gate stack comprising the dielectric layer of claim 1, and a gate electrode on the dielectric layer.

### Claim 26 (depends on 1)

A memory device comprising:
a transistor; and
a data storage element connected to the transistor, wherein the data storage element comprises the layer structure of claim 1.