# US 12,218,211 B2 · Structures of gate contact formation for vertical transistors

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- Number: US 12,218,211 B2
- Document ID: US12218211B2
- Status: Granted
- Kind: B2
- Application number: 18/233,293
- Filed: 2023-08-11
- Published: 2024-01-18
- Granted: 2025-02-04
- Earliest claimed: 2020-10-28
- Assignees: BeSang, Inc.
- Applicants: Sang-Yun Lee
- Inventors: Sang-Yun Lee
- Web page: https://patentgrep.com/patent/US12218211B2

## CPC

- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10B 12/05: {Making the transistor}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/01: Manufacture or treatment
- H10W 90/00: Package configurations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

## Claims

### Claim 1

A modified vertical transistor comprising:
a semiconductor pillar standing over a substrate;
a gate dielectric disposed over at least a portion of said semiconductor pillar;
a gate surrounding a middle portion of said semiconductor pillar over said gate dielectric;
an extended gate region disposed over a top of said semiconductor pillar and extending upward from said gate;
and wherein said semiconductor pillar comprises:
a first region of a first doping type in said middle portion of said semiconductor pillar;
a second region of a second doping type occupying a top portion of said semiconductor pillar, extending partly into said middle portion from said top portion, and contiguous with said first region; and
a third region of said second doping type occupying a bottom portion of said semiconductor pillar, extending partly into said middle portion from said bottom portion, and contiguous with said first region.

### Claim 2 (depends on 1)

The modified vertical transistor of claim 1, further comprising:
a dielectric film disposed over said substrate up to said bottom portion of said semiconductor pillar.

### Claim 3 (depends on 1)

The modified vertical transistor of claim 1, further comprising:
a gate bias line; and
a gate contact disposed on said extended gate region and coupled to said gate bias line.

### Claim 4 (depends on 1)

The modified vertical transistor of claim 1, further comprising:
a circuitry constructed on said substrate under said modified vertical transistor and electrically coupled to said gate.

### Claim 5

An array comprising:
a plurality of vertical transistors, each comprising;
a semiconductor pillar standing over a substrate;
a gate dielectric disposed over at least a portion of said semiconductor pillar; and
a gate surrounding a middle portion of said semiconductor pillar over said gate dielectric;
extended gate regions;
and wherein:
said array comprises at least one row;
each of said at least one row has at least one of said extended gate regions;
each of said extended gate regions extends upward from said gate over one of said plurality of vertical transistors to form a modified vertical transistor in each of said at least one row;
a space between said semiconductor pillars of immediate neighbors of said plurality of vertical transistors in each of said at least one row is sufficiently narrow and said gate film is sufficiently thick such that said plurality of vertical transistors are coupled at said gate along each of said at least one row; and
where said plurality of semiconductor pillars are arranged in said array with at least two rows, a space between said at least two rows is sufficiently wide and said gate film is sufficiently thin such that said plurality of vertical transistors are disconnected at said gate between said at least two rows.

### Claim 6 (depends on 5)

The array of claim 5, wherein said semiconductor pillar of each of said plurality of vertical transistors comprises:
a first region of a first doping type in said middle portion of said semiconductor pillar of each of said plurality of vertical transistors;
a second region of a second doping type occupying a top portion of said semiconductor pillar of each of said plurality of vertical transistors, extending partly into said middle portion from said top portion, and contiguous with said first region; and
a third region of said second doping type occupying a bottom portion of said semiconductor pillar of each of said plurality of vertical transistors, extending partly into said middle portion from said bottom portion, and contiguous with said first region.

### Claim 7 (depends on 5)

The array of claim 5, further comprising:
a dielectric film disposed over said substrate up to a bottom portion of said semiconductor pillar of each of said plurality of vertical transistors.

### Claim 8 (depends on 5)

The array of claim 5, further comprising:
gate bias lines;
gate contacts; and wherein:
each of said gate contacts is disposed on one of said extended gate regions;
each of said at least one row has one or more of said gate contacts; and
each of said gate bias lines is coupled to said one or more of said gate contacts in one of said at least one row.

### Claim 9 (depends on 5)

The array of claim 5, further comprising:
a plurality of storage capacitors, each with a first electrode and a second electrode; wherein:
each of said plurality of vertical transistors except said modified vertical transistors has said first electrode of one of said plurality of storage capacitors coupled to said semiconductor pillar to form a type of DRAM cell.

### Claim 10 (depends on 9)

The array of claim 9, further comprising:
a memory logic circuitry constructed under said plurality of vertical transistors for a memory operation; and wherein:
said memory logic circuitry is electrically coupled, for said memory operation, to said second electrode of each of said plurality of storage capacitors, to said extended gate regions, and to said semiconductor pillar of each of said plurality of vertical transistors except said modified vertical transistors; and
each of said plurality of vertical transistors except said modified vertical transistors serves as a switch for said memory operation.

### Claim 11 (depends on 5)

The array of claim 5, wherein:
said gate dielectric of each of said plurality of vertical transistors comprises a charge trapping layer to form a type of nonvolatile memory cell.

### Claim 12 (depends on 11)

The array of claim 11, further comprising:
a memory logic circuitry constructed under said plurality of vertical transistors for a memory operation; and wherein:
said memory logic circuitry is electrically coupled, for said memory operation, to said extended gate regions and to said semiconductor pillar of each of said plurality of vertical transistors except said modified vertical transistors; and
each of said plurality of vertical transistors except said modified vertical transistors serves as a switch for said memory operation.

### Claim 13

A semiconductor device comprising:
a plurality of vertical transistors, each comprising;
a semiconductor pillar standing over a substrate;
a gate dielectric disposed over at least a portion of said semiconductor pillar; and
a gate surrounding a middle portion of said semiconductor pillar over said gate dielectric;
a dielectric film disposed over said substrate up to a bottom portion of said semiconductor pillar of each of said plurality of vertical transistors;
a first extended gate region extending horizontally on said dielectric film from a bottom edge, but not from a top edge, of said gate of first at least one of said plurality of vertical transistors;
a second extended gate region extending from said gate over second at least one of said plurality of vertical transistors and disposed over a top of said semiconductor pillar of said second at least one of said plurality of vertical transistors;
and wherein:
said second at least one of said plurality of vertical transistors is modified to form said second extended gate;
and said semiconductor pillar of each of said plurality of vertical transistors comprises:
a first region of a first doping type in said middle portion of said semiconductor pillar of each of said plurality of vertical transistors;
a second region of a second doping type occupying a top portion of said semiconductor pillar of each of said plurality of vertical transistors, extending partly into said middle portion from said top portion, and contiguous with said first region; and
a third region of said second doping type occupying said bottom portion of said semiconductor pillar of each of said plurality of vertical transistors, extending partly into said middle portion from said bottom portion, and contiguous with said first region.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein:
said first at least one of said plurality of vertical transistors is in a first array;
said first array comprises a first group of vertical transistors arranged along a horizontal direction and selected from said plurality of vertical transistors; and
a space between said semiconductor pillars of immediate neighbors of said first group of vertical transistors is sufficiently narrow and said gate is sufficiently thick such that said first group of vertical transistors are coupled at said gate along said horizontal direction.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein:
said second at least one of said plurality of vertical transistors is in a second array;
said second array comprises a second group of vertical transistors arranged along a horizontal direction and selected from said plurality of vertical transistors; and
a space between said semiconductor pillars of immediate neighbors of said second group of vertical transistors is sufficiently narrow and said gate is sufficiently thick such that said second group of vertical transistors are coupled at said gate along said horizontal direction.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, further comprising:
a first contact disposed on said first extended gate region;
a second contact disposed on said second extended gate region;
a first gate bias line coupled to said first contact; and
a second gate bias line coupled to said second contact.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein:
said first gate bias line and said second gate bias line are coupled to a same voltage.