# US 12,218,210 B2 · Semiconductor device

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- Number: US 12,218,210 B2
- Document ID: US12218210B2
- Status: Granted
- Kind: B2
- Application number: 18/403,495
- Filed: 2024-01-03
- Published: 2024-04-25
- Granted: 2025-02-04
- Earliest claimed: 2020-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Cheng Chen; Chun-Hsiung Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12218210B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10W 20/033: {in openings in dielectrics}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/076: {in via holes or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/46: comprising air gaps
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/047: {by introducing additional elements therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

## Claims

### Claim 1

A device comprising:
a gate structure over a substrate;
a source/drain epitaxial structure adjacent the gate structure;
a metal oxide structure above the source/drain epitaxial structure;
a metal alloy layer over the source/drain epitaxial structure, wherein an entirety of a sidewall of the metal alloy layer is in contact with the metal oxide structure; and
a contact over the metal alloy layer and the metal oxide structure.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a contact etch stop layer lining sidewalls of the source/drain epitaxial structure, wherein the metal alloy layer is spaced apart from the contact etch stop layer by the metal oxide structure.

### Claim 3 (depends on 2)

The device of claim 2, wherein an air gap is defined by the contact etch stop layer, the contact, the metal alloy layer, and the metal oxide structure.

### Claim 4 (depends on 2)

The device of claim 2, wherein the contact etch stop layer is in contact with the contact.

### Claim 5 (depends on 1)

The device of claim 1, wherein a width of the contact is greater than a width of the metal alloy layer.

### Claim 6 (depends on 1)

The device of claim 1, wherein the metal oxide structure is in direct contact with a top surface of the source/drain epitaxial structure.

### Claim 7 (depends on 1)

The device of claim 1, wherein the contact comprises:
a barrier layer; and
a filling material over the barrier layer, wherein a portion of the metal oxide structure is embedded in the barrier layer.

### Claim 8

A device comprising:
a semiconductive layer over a substrate;
a gate structure surrounding the semiconductive layer;
a source/drain epitaxial structure interfacing with the semiconductive layer;
an epitaxial layer over the source/drain epitaxial structure;
a contact over the epitaxial layer;
metal oxide structures vertically between the source/drain epitaxial structure and the contact; and
a metal alloy layer over epitaxial layer and laterally between the metal oxide structures.

### Claim 9 (depends on 8)

The device of claim 8, wherein the metal oxide structures are in direct contact with a top surface of the source/drain epitaxial structure.

### Claim 10 (depends on 8)

The device of claim 8, wherein a top surface of the metal oxide structures is higher than a top surface of the metal alloy layer.

### Claim 11 (depends on 8)

The device of claim 8, wherein the contact is over the metal alloy layer.

### Claim 12 (depends on 8)

The device of claim 8, further comprising:
a contact etch stop layer lining sidewalls of the source/drain epitaxial structure, wherein the metal alloy layer is spaced apart from the contact etch stop layer by the metal oxide structures.

### Claim 13 (depends on 12)

The device of claim 12, wherein a top surface of the metal oxide structures is lower than a top surface of the contact etch stop layer.

### Claim 14 (depends on 8)

The device of claim 8, wherein the contact comprises:
a barrier layer; and
a filling material over the barrier layer, wherein portions of the metal oxide structures are embedded in the barrier layer.

### Claim 15

A device comprising:
a semiconductive layer over a substrate;
a gate structure surrounding the semiconductive layer;
a source/drain epitaxial structure adjacent the semiconductive layer;
an epitaxial layer over the source/drain epitaxial structure;
a metal oxide structure over the epitaxial layer; and
a contact over the epitaxial layer and the metal oxide structure, wherein a bottom surface of the contact is lower than a top surface the metal oxide structure and higher than a bottom surface of the metal oxide structure.

### Claim 16 (depends on 15)

The device of claim 15, wherein the contact comprises:
a barrier layer; and
a filling material over the barrier layer, wherein a portion of the metal oxide structure is embedded in the barrier layer.

### Claim 17 (depends on 15)

The device of claim 15, further comprising:
a contact etch stop layer covering a sidewall of the source/drain epitaxial structure but spaced apart from the epitaxial layer.

### Claim 18 (depends on 17)

The device of claim 17, wherein the top surface of the metal oxide structure is lower than a top surface of the contact etch stop layer.

### Claim 19 (depends on 17)

The device of claim 17, wherein a top surface of the metal oxide structure is lower than a top surface of the contact etch stop layer.

### Claim 20 (depends on 17)

The device of claim 17, wherein a maximal width of the epitaxial layer is less than a maximal width of the source/drain epitaxial structure.