# US 12,218,208 B2 · Display panel, display panel manufacturing method, and display device

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- Number: US 12,218,208 B2
- Document ID: US12218208B2
- Status: Granted
- Kind: B2
- Application number: 17/298,605
- Filed: 2019-12-06
- Published: 2022-01-27
- Granted: 2025-02-04
- Earliest claimed: 2018-12-24
- Assignees: Hkc Corporation Limited
- Applicants: Hkc Corporation Limited
- Inventors: Hejing Zhang
- Web page: https://patentgrep.com/patent/US12218208B2

## CPC

- H10D 30/6729: {characterised by the electrodes}
- H10D 64/01: Manufacture or treatment
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/021: {of multiple TFTs}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present application discloses a display panel, a display panel manufacturing method, and a display device. The display panel includes a source region and a drain region. A dielectric layer covering the source region and the drain region is provided with a first via hole and a second via hole separately. The first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole.

## Claims

### Claim 1

A display panel, comprising:
a substrate;
a buffer layer, formed on the substrate;
a semiconductor layer, formed on the buffer layer, wherein the semiconductor layer comprises a source region, a drain region, and a channel region, and the channel region is arranged between the source region and the drain region;
a gate insulating layer, formed at a position corresponding to the channel region of the semiconductor layer;
a gate metal layer, formed on the gate insulating layer; and
a dielectric layer, which is a single layer, wherein the dielectric layer covers the buffer layer, the semiconductor layer, and the gate metal layer, wherein the dielectric layer correspondingly covering the source region and the drain region defines via holes separately, the via holes each comprise a first via hole and a second via hole, the first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole; wherein a step is formed at a junction of the first via hole and the second via hole;
wherein the first via hole and the second via hole are coaxial; wherein both the first via hole and the second via hole are cylindrical holes.

### Claim 2 (depends on 1)

The display panel according to claim 1, wherein a depth of the first via hole and a depth of the second via hole are identical.

### Claim 3 (depends on 1)

The display panel according to claim 1, wherein a depth of the first via hole is less than a depth of the second via hole.

### Claim 4 (depends on 1)

The display panel according to claim 1, wherein the display panel further comprises a source, a drain, and a passivation layer; the source and the drain are respectively connected to the source region and the drain region through the via hole; and the passivation layer covers the source, the drain, and the dielectric layer.

### Claim 5

A display device, comprising a display panel, wherein the display panel comprises:
a substrate;
a buffer layer, formed on the substrate;
a semiconductor layer, formed on the buffer layer, wherein the semiconductor layer comprises a source region, a drain region, and a channel region, and the channel region is arranged between the source region and the drain region;
a gate insulating layer, formed at a position corresponding to the channel region of the semiconductor layer;
a gate metal layer, formed on the gate insulating layer; and
a dielectric layer, which is a single layer, wherein the dielectric layer covers the buffer layer, the semiconductor layer, and the gate metal layer, wherein the dielectric layer correspondingly covering the source region and the drain region defines via holes separately, the via holes each comprise a first via hole and a second via hole, the first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole; wherein a step is formed at a junction of the first via hole and the second via hole;
wherein the first via hole and the second via hole are coaxial; wherein both the first via hole and the second via hole are cylindrical holes.

### Claim 6 (depends on 5)

The display device according to claim 5, wherein the semiconductor layer is formed by deposition of at least one of a zinc oxide based semiconductor material, an indium oxide based semiconductor material, a tin oxide based semiconductor material, and another semiconductor material.

### Claim 7 (depends on 5)

The display device according to claim 5, wherein the dielectric layer is made of silicon dioxide.

### Claim 8

A display panel, comprising:
a substrate;
a buffer layer, formed on the substrate;
a semiconductor layer, formed on the buffer layer, wherein the semiconductor layer comprises a source region, a drain region, and a channel region, and the channel region is arranged between the source region and the drain region;
a gate insulating layer, formed at a position corresponding to the channel region of the semiconductor layer;
a gate metal layer, formed on the gate insulating layer; and
a dielectric layer, which is a single layer, wherein the dielectric layer covers the buffer layer, the semiconductor layer, and the gate metal layer, wherein the dielectric layer correspondingly covering the source region and the drain region defines via holes separately, the via holes each comprise a first via hole and a second via hole, the first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole; wherein a step is formed at a junction of the first via hole and the second via hole;
wherein the aperture of the first via hole gradually increases from the respective source region or drain region to the top of the first via hole; and the aperture of the second via hole gradually increases from the top of the first via hole to the top of the second via hole.