# US 12,218,207 B2 · Method for manufacturing semiconductor device

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- Number: US 12,218,207 B2
- Document ID: US12218207B2
- Status: Granted
- Kind: B2
- Application number: 18/412,609
- Filed: 2024-01-15
- Published: 2024-05-16
- Granted: 2025-02-04
- Earliest claimed: 2024-01-15
- Assignees: Innoscience (Suzhou) Technology Co., Ltd.
- Applicants: Innoscience (Suzhou) Technology Co., Ltd.
- Inventors: Qiyue Zhao; Wuhao Gao; Fengming Lin
- Web page: https://patentgrep.com/patent/US12218207B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/01: Manufacture or treatment
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10W 74/01: Manufacture or treatment
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device including steps as follows is provided. A first nitride-based semiconductor layer is formed over a substrate. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A gate electrode is formed over the second nitride-based semiconductor layer. A first passivation layer is formed on the second nitride-based semiconductor layer to cover the gate electrode. A first blanket field plate is formed on the first passivation layer. The first blanket field plate is patterned to form a first field plate above the gate electrode using a wet etching process. A second passivation layer is formed on the first passivation layer to cover the first field plate. A second blanket field plate is formed on the second passivation layer. The second blanket field plate is patterned to form a second field plate above the first field plate using a dry etching process.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a first nitride-based semiconductor layer over a substrate;
forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;
forming a gate electrode over the second nitride-based semiconductor layer;
forming a first passivation layer on the second nitride-based semiconductor layer to cover the gate electrode;
forming a first blanket field plate on the first passivation layer;
patterning the first blanket field plate to form a first field plate above the gate electrode using a wet etching process;
forming a second passivation layer on the first passivation layer to cover the first field plate;
forming a second blanket field plate on the second passivation layer; and
patterning the second blanket field plate to form a second field plate above the first field plate using a dry etching process.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a third passivation layer to cover the second field plate.

### Claim 3 (depends on 1)

The method of claim 1, wherein patterning the first blanket field plate is performed such that the first field plate laterally spans across the gate electrode.

### Claim 4 (depends on 1)

The method of claim 1, wherein patterning the second blanket field plate is performed such that the second field plate laterally spans across the first field plate.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a pair of source/drain (S/D) electrodes over the second nitride-based semiconductor layer, such that the gate electrode, the first field plate, and the second field plate are located between the S/D electrodes.