# US 12,218,206 B2 · Power semiconductor device and method of manufacturing the same

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- Number: US 12,218,206 B2
- Document ID: US12218206B2
- Status: Granted
- Kind: B2
- Application number: 17/685,886
- Filed: 2022-03-03
- Published: 2022-10-06
- Granted: 2025-02-04
- Earliest claimed: 2021-03-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sunkyu Hwang; Jongseob Kim
- Web page: https://patentgrep.com/patent/US12218206B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/01: Manufacture or treatment
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 64/111: {Field plates}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a power semiconductor device includes forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate hole, a source hole, and a drain hole penetrating the passivation layer in a same process step; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern may be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern may have a step difference.

## Claims

### Claim 1

A method of manufacturing a power semiconductor device, the method comprising:
forming a channel separation pattern on a substrate;
forming a passivation layer on the substrate and the channel separation pattern; and
forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern penetrating the passivation layer in a same process step,
wherein the gate electrode pattern is formed on the channel separation pattern, and
a side surface of the gate electrode pattern and a side surface of the channel separation pattern have a step difference.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the gate electrode pattern, the source electrode pattern, and the drain electrode pattern includes:
forming a gate hole, a source hole, and a drain hole penetrating the passivation layer;
filling the gate hole, the source hole, and the drain hole by depositing a conductive material layer on the passivation layer; and
patterning the conductive material layer,
wherein the gate electrode pattern, the source electrode pattern, and the drain electrode pattern are formed in the gate hole, the source hole, and the drain hole, respectively.

### Claim 3 (depends on 2)

The method of claim 2,
wherein the gate electrode pattern includes an electric field relaxation region extending toward the drain electrode pattern along an upper surface of the passivation layer, and
a distance between the electric field relaxation region and the drain electrode pattern is less than a distance between the channel separation pattern and the drain electrode pattern.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a Schottky barrier metal pattern between the channel separation pattern and the gate electrode pattern.

### Claim 5 (depends on 4)

The method of claim 4,
wherein the Schottky barrier metal pattern extends between the gate electrode pattern and the passivation layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming:
an electric field relaxation pattern between the gate electrode pattern and the drain electrode pattern,
wherein the electric field relaxation pattern is formed in the same process step as the gate electrode pattern, the source electrode pattern, and the drain electrode pattern.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming of the gate electrode pattern, the source electrode pattern, the drain electrode pattern, and the electric field relaxation pattern includes:
forming a gate hole, a source hole, and a drain hole penetrating the passivation layer;
filling the gate hole, the source hole, and the drain hole by depositing a conductive material layer on the passivation layer; and
patterning the conductive material layer.

### Claim 8 (depends on 1)

The method of claim 1,
wherein the gate electrode pattern, the source electrode pattern, and the drain electrode pattern include a same conductive material.

### Claim 9 (depends on 1)

The method of claim 1,
wherein the channel separation pattern includes p-type gallium nitride (GaN).

### Claim 10

A power semiconductor device comprising:
a substrate including a channel;
a channel separation pattern on the substrate; a passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate hole, a source hole, and a drain hole penetrating the passivation layer; and
a gate electrode pattern, a source electrode pattern, and a drain electrode pattern in the gate hole, the source hole, and the drain hole, respectively, and extending onto an upper surface of the passivation layer, wherein a side surface of the gate electrode pattern in the gate hole and a side surface of the channel separation pattern have a step difference, and
wherein the gate electrode pattern, the source electrode pattern, and the drain electrode pattern include a same conductive material.

### Claim 11 (depends on 10)

The power semiconductor device of claim 10, wherein
the source electrode pattern does not extend over the gate electrode pattern.

### Claim 12 (depends on 10)

The power semiconductor device of claim 10, further comprising:
a Schottky barrier metal pattern between the gate electrode pattern and the channel separation pattern,
wherein the Schottky barrier metal pattern includes a conductive material different from those of the gate electrode pattern, the source electrode pattern, and the drain electrode pattern.

### Claim 13 (depends on 10)

The power semiconductor device of claim 10,
wherein the channel separation pattern includes p-type gallium nitride (GaN).

### Claim 14 (depends on 10)

The power semiconductor device of claim 10,
wherein the gate electrode pattern includes an electric field relaxation region extending toward the drain electrode pattern along an upper surface of the passivation layer, and
a distance between the electric field relaxation region and the drain electrode pattern is less than a distance between the channel separation pattern and the drain electrode pattern.

### Claim 15 (depends on 10)

The power semiconductor device of claim 10, further comprising:
an electric field relaxation pattern between the gate electrode pattern and the drain electrode pattern.

### Claim 16

A power semiconductor device comprising:
a substrate including a channel;
a channel separation pattern on the substrate;
a passivation layer on the substrate and the channel separation pattern, the passivation layer including a gate hole, a source hole, and a drain hole penetrating the passivation layer; and
a gate structure, a source electrode pattern, and a drain electrode pattern in the gate hole, the source hole, and the drain hole, respectively, and extending onto an upper surface of the passivation layer,
wherein a width of a bottom surface of the gate structure in a first direction is less than a width of an upper surface of the channel separation pattern in the first direction,
wherein the gate structure includes a gate electrode pattern,
wherein the gate electrode pattern, the source electrode pattern, and the drain electrode pattern include a same conductive material, and
the source electrode pattern does not vertically overlap the gate electrode pattern.

### Claim 17 (depends on 16)

The power semiconductor device of claim 16,
wherein the gate electrode pattern directly contacts the channel separation pattern, and
a side surface of a portion of the gate electrode pattern in the gate hole and a side surface of the channel separation pattern have a step difference.

### Claim 18 (depends on 16)

The power semiconductor device of claim 16,
wherein the gate structure includes a Schottky barrier metal pattern on the channel separation pattern.

### Claim 19 (depends on 18)

The power semiconductor device of claim 18, wherein
a side surface of a portion of the Schottky barrier metal pattern in the gate hole and a side surface of the channel separation pattern have a step difference.

### Claim 20 (depends on 16)

The power semiconductor device of claim 16,
wherein the channel separation pattern includes p-type gallium nitride (GaN).