# US 12,218,205 B2 · 2D-channel transistor structure with source-drain engineering

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- Number: US 12,218,205 B2
- Document ID: US12218205B2
- Status: Granted
- Kind: B2
- Application number: 18/354,820
- Filed: 2023-07-19
- Published: 2023-11-09
- Granted: 2025-02-04
- Earliest claimed: 2020-08-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Dhanyakumar Mahaveer Sathaiya; Khaderbad Mrunal Abhijith; Tzer-Min Shen
- Web page: https://patentgrep.com/patent/US12218205B2

## CPC

- H10D 62/80: characterised by the materials
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/82: Heterojunctions
- H10D 62/881: {being a two-dimensional material}
- H10D 62/882: {Graphene}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

## Claims

### Claim 1

A semiconductor device, comprising:
a channel member including a first channel layer and a second channel layer over the first channel layer;
a dielectric feature inserted between the second channel layer and the first channel layer;
a gate structure over the channel member; and
a source feature and a drain feature of a semiconductor material,
wherein the second channel layer includes a two-dimensional material, and wherein the semiconductor material of the source and drain features electrically connects to the first and second channel layers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the two-dimensional material includes graphene, tungsten sulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum sulfide (MoS2), molybdenum telluride (MoTe2), black phosphorus, or molybdenum selenide (MoSe2).

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein
the gate structure includes a gate stack and a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the gate stack; and
the second channel layer spans between the first spacer and the second spacer of the gate spacer layer.

### Claim 5

A semiconductor device, comprising:
a plurality of semiconductor layers disposed on a substrate, vertically stacked and distanced from each other;
a plurality of two-dimensional (2D) material layers disposed on a top surface and a bottom surface of each of the plurality of semiconductor layers, respectively;
a source feature and a drain feature electrically connected to the each of the plurality of semiconductor layers and each of the plurality of 2D material layers, wherein the source feature and drain feature include a semiconductor material; and
a gate structure over the substrate and extending to wrap around the each of the plurality of semiconductor layers and the each of the plurality of 2D material layers.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein
the plurality of 2D material layers include portions wrapping around the each of the plurality of semiconductor layers; and
the gate structure wraps each of the portions of the 2D material layer.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein
the plurality of 2D material layers include one of graphene, tungsten sulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum sulfide (MoS2), molybdenum telluride (MoTe2), black phosphorus, and molybdenum selenide (MoSe2); and
the plurality of semiconductor layers include one of silicon, germanium, a III-V semiconductor, and a II-VI semiconductor.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the gate structure includes a gate stack and a first and second gate spacers disposed on two sidewalls of the gate stack, wherein the gate stack spans between the first and second gate spacers, and wherein the gate first and second spacers contact a topmost one of the plurality of 2D material layers.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising inner spacers disposed between the source feature and the gate stack, wherein
the inner spacers are underlying the first and second gate spacers and are vertically aligned with the first and second gate spacers, respectively, and
each of the inner spacers vertically spans between adjacent two of the plurality of 2D material layers.

### Claim 10

A method, comprising:
providing a workpiece having a semiconductor structure;
depositing a two-dimensional (2D) material layer over the semiconductor structure;
patterning the semiconductor structure to form trenches in source/drain regions;
epitaxially growing a semiconductor material to fill in the trenches, thereby forming a source feature and a drain feature, wherein the source feature and the drain feature are electrically connected to the semiconductor structure and the 2D material layer, and wherein the source feature and drain feature include a semiconductor material; and
forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature, wherein the gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor, and wherein the semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

### Claim 11 (depends on 10)

The method of claim 10, wherein
the semiconductor structure comprises silicon, germanium, a III-V semiconductor, or a II-VI semiconductor; and
the 2D material layer includes one of graphene, tungsten sulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum sulfide (MoS2), molybdenum telluride (MoTe2), black phosphorus, and molybdenum selenide (MoSe2).

### Claim 12 (depends on 10)

The method of claim 10, wherein
the patterning of the semiconductor structure further includes patterning the 2D material layer; and
the epitaxially growing of the semiconductor material includes epitaxially growing the semiconductor material in direct contact with edges of the 2D material layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein
the gate structure includes a gate stack and a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the gate stack; and
the patterning of the 2D material layer includes patterning the 2D material layer such that the patterned 2D material layer spans between the first spacer and the second spacer of the gate spacer layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the patterning of the 2D material layer includes patterning the 2D material layer such that opposite edges of the patterned 2D material layer are aligned with outer sides of the first and second spacers, respectively.

### Claim 15 (depends on 10)

The method of claim 10, further comprising forming a dielectric feature inserted between the 2D material layer and the semiconductor structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming a dielectric feature includes
forming a sacrificial semiconductor layer on the semiconductor structure before the depositing of the 2D material layer; and
replacing the sacrificial semiconductor layer with a dielectric layer through the trenches after the patterning of the semiconductor structure to form the trenches in source/drain regions.

### Claim 17 (depends on 16)

The method of claim 16, wherein the replacing the sacrificial semiconductor layer with a dielectric layer includes performing a selective oxidization process to oxidize the sacrificial semiconductor layer to form a semiconductor oxide layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the sacrificial semiconductor layer is a silicon germanium layer.

### Claim 19 (depends on 10)

The method of claim 10, wherein the depositing of the 2D material layer includes
forming a dummy gate stack over the semiconductor structure and a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the dummy gate stack;
removing the dummy gate stack after the forming of the source feature and the drain feature, resulting in a gate trench defined by the first and second spacers, the semiconductor structure is exposed within the gate trench; and
selectively depositing the 2D material layer on the semiconductor structure exposed within the gate trench such that the 2D material layer spans between inner sides of the first and second spacers, respectively.

### Claim 20 (depends on 19)

The method of claim 19, wherein the forming of the gate structure includes forming the gate structure on the 2D material layer within the gate trench.