# US 12,218,203 B2 · Integrated circuit structure and method with solid phase diffusion

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- Number: US 12,218,203 B2
- Document ID: US12218203B2
- Status: Granted
- Kind: B2
- Application number: 18/360,168
- Filed: 2023-07-27
- Published: 2023-11-16
- Granted: 2025-02-04
- Earliest claimed: 2015-12-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Yi Peng; Ling-Yen Yeh; Chi-Wen Liu; Chih-Sheng Chang; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12218203B2

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

## Claims

### Claim 1

A device comprising:
a first fin active region and a second fin active region disposed on a substrate;
a first dielectric isolation structure disposed on the substrate and interfacing with the first fin active region and the second fin active region;
a first dopant region disposed within the first dielectric isolation structure and extending to a first depth within the first dielectric isolation structure, the first dopant region including a first dopant; and
a second dopant region disposed within the first dielectric isolation structure and extending to a second depth within the first dielectric isolation structure, the second depth being different than first depth such that one of the first dopant region and the second dopant region extends within the first dielectric isolation structure towards the substrate to a deeper depth than the other of the first dopant region and the second dopant region, the second dopant region including a second dopant that is different than the first dopant.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first dopant is a p-type dopant and the second dopant is an n-type dopant.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first dopant region extends within the first dielectric isolation structure towards the substrate to a deeper depth than the second dopant region.

### Claim 4 (depends on 2)

The device of claim 2, wherein the second dopant region extends within the first dielectric isolation structure towards the substrate to a deeper depth than the first dopant region.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first dopant is spaced apart from the second dopant region such that a portion of the first dielectric isolation structure that is free of either of the first and second dopant regions is positioned between the first and second dopant regions.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first fin active region has a first width and the second fin active region has a second width that is different than the first width.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
a plurality of first gate structures disposed on the first fin active region, and
a plurality of second gate structures disposed on the second fin active region.

### Claim 8 (depends on 1)

The device of claim 1, further comprising:
a second dielectric isolation structure disposed on the substrate and interfacing with the first fin active region; and
a third dopant region disposed within the first dielectric isolation structure and extending to a third depth within the first dielectric isolation structure, the first dopant region including the first dopant.

### Claim 9

A device comprising:
a first fin active region and a second fin active region disposed on a substrate, wherein the first fin active region has a different width than the second fin active region;
a first dielectric isolation structure disposed on the substrate between the first fin active region and the second fin active region;
a first dopant region and a second dopant region disposed within the first dielectric isolation structure, the second dopant region being spaced apart from the first dopant region, wherein one of the first dopant region and the second dopant region extends within the first dielectric isolation structure towards the substrate to a deeper depth than the other of the first dopant region and the second dopant region;
a first semiconductor material layer disposed over the first fin active region and interfacing with the first dopant region; and
a second semiconductor material layer disposed over the second fin active region and interfacing with the second dopant region, wherein the second semiconductor material layer has a different composition than the first semiconductor material layer.

### Claim 10 (depends on 9)

The device of claim 9, wherein the first dopant region includes a p-type dopant and the second dopant region includes an n-type dopant.

### Claim 11 (depends on 9)

The device of claim 9, further comprising:
a first anti-punch through (APT) feature disposed in the first fin active region and interfacing with the first dopant region; and
a second APT feature disposed in the second fin active region and interfacing with the second dopant region.

### Claim 12 (depends on 11)

The device of claim 11, wherein the first APT feature extends within the first fin active region to a first height above the substrate, and
wherein the second APT feature extends within the second fin active region to a second height above the substrate that is different than the first height.

### Claim 13 (depends on 12)

The device of claim 12, further comprising:
a second dielectric isolation structure disposed on the substrate adjacent the first fin active region;
a third dielectric isolation structure disposed on the substrate adjacent the second fin active region,
a third dopant region disposed within the second dielectric isolation structure, the third dopant region extending within the second dielectric isolation structure towards the substrate to a first depth; and
a fourth dopant region disposed within the third dielectric isolation structure, the fourth dopant region extending within the third dielectric isolation structure towards the substrate to a second depth, the second depth being different than the first depth.

### Claim 14 (depends on 13)

The device of claim 13, wherein the first APT feature interfaces with first dopant region and the third dopant region, and
wherein the second APT feature interfaces with the second dopant region and the fourth dopant region.

### Claim 15 (depends on 14)

The device of claim 14, wherein the first dopant region, the third dopant region and the first APT feature include a first dopant, and
wherein the second dopant region, the fourth dopant region and the second APT feature include a second dopant that has a different material composition than the first dopant.

### Claim 16

A semiconductor device, comprising:
a first fin and a second fin disposed on a substrate;
an isolation feature disposed on the substrate and comprising a first sidewall interfacing the first fin and a second sidewall interfacing the second fin;
a first semiconductor layer disposed over the first fin; and
a second semiconductor layer disposed over the second fin,
wherein the isolation feature comprises a first dopant region along the first sidewall and a second dopant region along the second sidewall,
wherein one of the first dopant region and the second dopant region extends within the isolation feature towards the substrate to a deeper depth than the other of the first dopant region and the second dopant region,
wherein the first semiconductor layer interfaces the first dopant region,
wherein the second semiconductor layer interfaces the second dopant region,
wherein the second semiconductor layer has a different composition than the first semiconductor layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16,
wherein the first dopant region comprises boron,
wherein the second dopant region comprises phosphorus.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the first semiconductor layer comprises gallium arsenic or indium phosphorous.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the second semiconductor layer comprises germanium or diamond.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, further comprising:
a first anti-punch through (APT) feature disposed in the first fin and interfacing with the first dopant region; and
a second APT feature disposed in the second fin and interfacing with the second dopant region.