# US 12,218,202 B2 · Semiconductor device incorporating a substrate recess

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- Number: US 12,218,202 B2
- Document ID: US12218202B2
- Status: Granted
- Kind: B2
- Application number: 17/477,004
- Filed: 2021-09-16
- Published: 2023-03-16
- Granted: 2025-02-04
- Earliest claimed: 2021-09-16
- Assignees: Wolfspeed, Inc.
- Applicants: Wolfspeed, Inc.
- Inventors: Evan Jones; Saptha Sriram; Kyle Bothe
- Web page: https://patentgrep.com/patent/US12218202B2

## CPC

- H10D 62/357: {of FETs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate, wherein an upper surface of the substrate comprises a recess region;
a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region; and
a gate contact, a drain contact, and a source contact on the semiconductor structure,
wherein the recess region is in between the gate contact and the source contact and does not vertically overlap the drain contact,
wherein the semiconductor device comprises a high electron mobility transistor (HEMT) and the semiconductor structure comprises a channel layer and a barrier layer on the channel layer, and the channel layer extends continuously from underneath the source contact to underneath the drain contact,
wherein the portion of the semiconductor structure that is within the recess region is an undoped Group III-nitride layer, and
wherein the substrate comprises an n-type semiconductor substrate that includes a p-type impurity region adjacent the recess region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the p-type impurity region does not vertically overlap the drain contact.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the p-type impurity region is on at least one sidewall and/or a bottom surface of the recess region.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the recess region vertically overlaps a portion of the semiconductor structure that is in between the source contact and the gate contact.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the upper surface of the substrate comprises silicon carbide.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the recess region does not vertically overlap the gate contact or the source contact.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the p-type impurity region only vertically overlaps a portion of the source contact.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the p-type impurity region only vertically overlaps a portion of the gate contact.

### Claim 9

A semiconductor device comprising:
a substrate, wherein an upper surface of the substrate comprises a recess region;
a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region; and
a gate contact, a drain contact, and a source contact on the semiconductor structure,
wherein the substrate and the portion of the semiconductor structure within the recess region form a heterojunction,
wherein the semiconductor device is configured so that a two-dimensional electron gas (“2DEG”) layer that extends continuously from underneath the source contact to underneath the drain contact is induced in the semiconductor structure during on-state operation,
wherein the recess region does not vertically overlap any of the source contact, the gate contact or the drain contact
wherein portions of the substrate that comprise sidewalls of the recess region and a bottom of the recess region are implanted with first conductivity type dopants.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the portion of the semiconductor structure that is within the recess region is an undoped Group III-nitride layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the substrate comprises an n-type semiconductor substrate.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the portions of the substrate that comprise the sidewalls of the recess region and the bottom of the recess region that are implanted with the first conductivity type dopants only vertically overlaps a portion of the source contact.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the portions of the substrate that comprise the sidewalls of the recess region and the bottom of the recess region that are implanted with the first conductivity type dopants only vertically overlaps a portion of the gate contact.