# US 12,218,201 B2 · Device architectures with tensile and compressive strained substrates

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- Number: US 12,218,201 B2
- Document ID: US12218201B2
- Status: Granted
- Kind: B2
- Application number: 17/347,417
- Filed: 2021-06-14
- Published: 2022-12-15
- Granted: 2025-02-04
- Earliest claimed: 2021-06-14
- Assignees: National University of Singapore; Soitec
- Applicants: Soitec; National University of Singapore
- Inventors: Bich-Yen Nguyen; Christophe Maleville; Walter Schwarzenbach; Gong Xiao; Aaron Thean; Chen Sun; Haiwen Xu
- Web page: https://patentgrep.com/patent/US12218201B2

## CPC

- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/214: {Recoil-implantation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.

## Claims

### Claim 1

A semiconductor structure, comprising:
a base substrate;
an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and
an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, silicon germanium or any combination thereof, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising:
a first plurality of volumes of semiconductor material having a tensile strain of at least 0.6%; and
a second plurality of volumes of semiconductor material having a compressive strain of at least −0.6%, the second plurality of volumes of semiconductor material comprising a compressive strained silicon germanium material positioned on recrystallized silicon obtained from crystallization of ion-implanted amorphous silicon.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a plurality of nFETs, each nFET comprising a channel region including a volume of the tensile strained semiconductor material of the first plurality and a plurality of pFETs, each pFET comprising a channel region including a volume of the compressive strained semiconductor material of the second plurality.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the tensile strain is about 0.8% and the compressive strain is about −0.8%.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein each volume of semiconductor material of the at least two pluralities has a comb structure.

### Claim 5

A semiconductor device, comprising:
a semiconductor-on-insulator substrate including a base substrate, a buried insulator layer, and an active layer comprising a fully depleted semiconductor material; and
a plurality of transistors in a common plane, each transistor of the plurality of transistors comprising a channel region in a volume of the fully depleted semiconductor material of the active layer of the semiconductor-on-insulator substrate, wherein plurality of transistors comprises:
nFETs having tensile strained channel regions; and
pFETs having compressive strained channel regions, wherein the compressive strained channel regions comprise a compressive strained silicon germanium material positioned on recrystallized silicon obtained from crystallization of ion-implanted amorphous silicon.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the channel regions of the transistors of the plurality of transistors are located within a volume of the fully depleted semiconductor material having a comb structure including a horizontally extending spine and vertically extending tines extending perpendicularly from the spine, the tines having a first thickness of between about 10 nanometers and about 30 nanometers, the spine having a second thickness between about 0 nanometers and about 10 nanometers.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein adjacent tines of the comb structure are separated from one another in a direction parallel to the spine of the comb structure by a distance between about 5 nanometers and about 15 nanometers.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the tensile strained channel regions of the nFETs comprise tensile strained silicon, and the compressive strained channel regions of the pFETs comprise the compressive strained silicon germanium.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, further comprising back gates under each transistor of the plurality of transistors.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the back gates comprise local phosphorus or arsenic or boron implanted under a buried oxide.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, further comprising a comb structure configured to provide back-gate coupling.

### Claim 12 (depends on 5)

The semiconductor device of claim 5, wherein a dosage of the implanted ions in the compressive strained channel regions is between about 1×1014 ions/cm2 and about 4×1014 ions/cm2.

### Claim 13 (depends on 1)

The semiconductor structure of claim 1, wherein a dosage of the implanted ions in the second plurality of volumes of semiconductor material is between about 1×1014 ions/cm2 and about 4×1014 ions/cm2.