# US 12,218,200 B2 · Semiconductor device and method

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- Number: US 12,218,200 B2
- Document ID: US12218200B2
- Status: Granted
- Kind: B2
- Application number: 18/359,695
- Filed: 2023-07-26
- Published: 2023-11-30
- Granted: 2025-02-04
- Earliest claimed: 2021-03-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Yi Lee; Cheng-Lung Hung; Chi On Chui
- Web page: https://patentgrep.com/patent/US12218200B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.

## Claims

### Claim 1

A method comprising:
forming a first nanostructure and a second nanostructure over a substrate, the second nanostructure being over the first nanostructure, the first nanostructure comprising a first channel region, the second nanostructure comprising a second channel region;
forming a first gate dielectric layer on the first channel region and the second channel region;
forming a first work function tuning layer on the first gate dielectric layer, the first work function tuning layer extending from the first gate dielectric layer on the first channel region to the first gate dielectric layer on the second channel region, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, wherein the first n-type work function metal comprises zirconium;
forming a first barrier layer on the first work function tuning layer;
forming a glue layer on the first barrier layer; and
forming a fill layer on the glue layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the fill layer does not extend between the first and second nanostructures.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
forming a second barrier layer on the first gate dielectric layer, the first work function tuning layer being formed on the second barrier layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first work function tuning layer comprises zirconium aluminum carbide.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a third nanostructure and a fourth nanostructure over the substrate, the fourth nanostructure being over the third nanostructure, the third nanostructure comprising a third channel region, the fourth nanostructure comprising a fourth channel region;
forming a second gate dielectric layer on the third channel region and the fourth channel region; and
forming the first work function tuning layer on the second gate dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first work function tuning layer is formed by an atomic layer deposition process comprising cyclically dispensing a zirconium source precursor and an aluminum source precursor into a deposition chamber.

### Claim 7 (depends on 6)

The method of claim 6, wherein the atomic layer deposition process is performed at a temperature in a range of 200° C. to 500° C. and at a pressure in a range of 0.5 torr to 45 torr.

### Claim 8

A device comprising:
a first nanostructure and a second nanostructure over a substrate, the second nanostructure being over the first nanostructure, the first nanostructure comprising a first channel region, the second nanostructure comprising a second channel region;
a first gate dielectric layer on the first channel region and the second channel region;
a first work function tuning layer on the first gate dielectric layer, the first work function tuning layer extending from the first gate dielectric layer on the first channel region to the first gate dielectric layer on the second channel region, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, wherein the first n-type work function metal comprises zirconium;
a first barrier layer on the first work function tuning layer;
a glue layer on the first barrier layer; and
a fill layer on the glue layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first work function tuning layer comprises zirconium aluminum carbide.

### Claim 10 (depends on 8)

The device of claim 8, further comprising:
a third nanostructure and a fourth nanostructure over the substrate, the fourth nanostructure being over the third nanostructure, the third nanostructure comprising a third channel region, the fourth nanostructure comprising a fourth channel region;
a second gate dielectric layer on the third channel region and the fourth channel region; and
a second work function tuning layer on the second gate dielectric layer.

### Claim 11 (depends on 10)

The device of claim 10, wherein the glue layer and the second work function tuning layer have a same material composition.

### Claim 12 (depends on 10)

The device of claim 10, wherein the second work function tuning layer is on the glue layer.

### Claim 13 (depends on 10)

The device of claim 10 further comprising:
a second barrier layer on the first gate dielectric layer, the first work function tuning layer being on the second barrier layer.

### Claim 14 (depends on 10)

The device of claim 10, wherein the first gate dielectric layer and the second gate dielectric layer have a same material composition.

### Claim 15 (depends on 8)

The device of claim 8, further comprising a second barrier layer between the first gate dielectric layer and the first work function tuning layer, wherein the second barrier layer comprises titanium nitride, silicon-doped titanium nitride, or tantalum nitride.

### Claim 16 (depends on 8)

The device of claim 8, wherein the first work function tuning layer has a thickness in a range of 5 Å to 50 Å, and wherein a ratio of the thickness of the first work function tuning layer to a thickness of the first gate dielectric layer is in a range from 0.5 to 7.

### Claim 17

A method comprising:
forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region and a second channel region, the second set of nanostructures comprising a third channel region and a fourth channel region;
forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first and second channel regions, the second portion deposited on the third and fourth channel regions;
forming an n-type work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer, the n-type work function tuning layer extending from the gate dielectric layer on the first channel region to the gate dielectric layer on the second channel region, wherein the n-type work function tuning layer comprises zirconium aluminum carbide, hafnium aluminum carbide, niobium aluminum carbide, or combinations thereof;
forming a first barrier layer on the n-type work function tuning layer;
removing the first barrier layer and the n-type work function tuning layer from the second portion of the gate dielectric layer;
forming a p-type work function tuning layer on the first barrier layer on the first set of nanostructures and the second portion of the gate dielectric layer, the p-type work function tuning layer extending from the gate dielectric layer on the third channel region to the gate dielectric layer on the fourth channel region; and
forming a fill layer on the p-type work function tuning layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the fill layer does not extend between adjacent nanostructures of the first set of nanostructures.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming inner spacers on sidewalls of the first set of nanostructures and the second set of nanostructures prior to forming the gate dielectric layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the n-type work function tuning layer is formed to a thickness sufficient to cause merging of portions of the n-type work function tuning layer between adjacent nanostructures of the first set of nanostructures.