# US 12,218,196 B2 · Semiconductor device and method of manufacture

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- Number: US 12,218,196 B2
- Document ID: US12218196B2
- Status: Granted
- Kind: B2
- Application number: 17/670,924
- Filed: 2022-02-14
- Published: 2023-08-17
- Granted: 2025-02-04
- Earliest claimed: 2022-02-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Chang Lin; Chun-Hung Wu; Liang-Yin Chen; Huicheng Chang; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12218196B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/504: {wherein the stacked channels have different properties}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

## Claims

### Claim 1

A method comprising:
depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers;
forming a dummy gate on the multi-layer stack;
forming a first spacer on a sidewall of the dummy gate;
performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose;
performing a second implantation process to form a second doped region, wherein the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, wherein the second implant energy is greater than the first implant energy, and wherein the first implant dose is different from the second implant dose;
after performing the first implantation process and the second implantation process, forming a second spacer on a sidewall of the first spacer;
forming a first recess in the multi-layer stack adjacent the second spacer; and
forming an epitaxial source/drain region in the first recess.

### Claim 2 (depends on 1)

The method of claim 1, wherein performing the first implantation process and the second implantation process comprises implanting arsenic (As), phosphorous (P), antimony (Sb), boron di-fluoride (BF2), or boron (B) into exposed portions of the multi-layer stack.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first spacer and the second spacer have a thickness that is in a range from 3 nm to 5 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein dopant concentrations of the first doped region and the second doped region are in a range from 1×1017 atoms/cm3 to 1×1021 atoms/cm3.

### Claim 5 (depends on 4)

The method of claim 4, wherein a dopant concentration of the epitaxial source/drain region is greater than dopant concentrations of the first doped region and the second doped region.

### Claim 6 (depends on 1)

The method of claim 1, wherein after the first implantation process and the second implantation process, dopants from the first doped region migrate in a direction parallel to a top surface of the semiconductor substrate into a first portion of a first channel layer beneath the dummy gate, and dopants from the second doped region move in a direction parallel to the top surface of the semiconductor substrate into a second portion of a second channel layer beneath the dummy gate, wherein the second channel layer is below the first channel layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first implant dose is greater than the second implant dose, and wherein a first width of the first portion of the first channel layer is greater than a second width of the second portion of the second channel layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein the first implant dose is less than the second implant dose, and wherein a first width of the first portion of the first channel layer is less than a second width of the second portion of the second channel layer.

### Claim 9

A method comprising:
forming a dummy gate on a first channel region of a first channel layer and a second channel region of a second channel layer, the first channel layer and the second channel layer disposed above a semiconductor substrate;
forming a first spacer on a sidewall of the dummy gate;
performing a first implantation process to implant dopants in the first channel layer to form first doped portions on first ends of the first channel region;
performing a second implantation process to implant dopants in the second channel layer to form second doped portions on second ends of the second channel region, wherein during the first implantation process and the second implantation process the dummy gate and the first spacers are used as an implant mask, wherein each of the first doped portions and the second doped portions have a gradient-doped profile; and
after performing the first implantation process and the second implantation process, forming a second spacer on a sidewall of the first spacer.

### Claim 10 (depends on 9)

The method of claim 9, wherein dopant concentrations of the first doped portions and the second doped portions are in a range from 1×1018 atoms/cm3 to 1×1020 atoms/cm3.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first implantation process forms third doped portions in the first channel layer, each third doped portion being adjacent to a corresponding first doped portion, and wherein the second implantation process forms fourth doped portions in the second channel layer, each fourth doped portion being adjacent to a corresponding second doped portion, wherein dopant concentrations of the third doped portions and the fourth doped portions are greater than dopant concentrations of the first doped portions and the second doped portions.

### Claim 12 (depends on 11)

The method of claim 11, wherein a dopant concentration of each respective first doped portion decreases in a direction extending away from a center of the respective first doped portion to the first channel region, and wherein a dopant concentration of each respective second doped portion decreases in a direction extending away from a center of the respective second doped portion to the second channel region.

### Claim 13 (depends on 9)

The method of claim 9, wherein the first implantation process is performed with a first implant energy and a first implant dose, and the second implantation process is performed with a second implant energy and a second implant dose, wherein the second implant energy is greater than the first implant energy, and wherein the first implant dose is different from the second implant dose.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second implant dose is greater than the first implant dose, and a first width of each of the first doped portions is less than a second width of each of the second doped portions.

### Claim 15 (depends on 13)

The method of claim 13, wherein the second implant dose is less than the first implant dose, and a first width of each of the first doped portions is greater than a second width of each of the second doped portions.

### Claim 16

A method comprising:
forming a dummy gate on a multi-layer stack, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers;
forming a first spacer on a sidewall of the dummy gate;
performing a first implantation process to form first doped portions on first ends of a first channel region of a first channel layer of the plurality of channel layers;
performing a second implantation process to form second doped portions on second ends of a second channel region of a second channel layer of the plurality of channel layers;
forming a first recess in the multi-layer stack adjacent the dummy gate;
forming a semiconductor material in a bottom portion of the first recess;
performing a third implantation process to introduce dopants into the semiconductor material; and
forming an epitaxial source/drain region over the semiconductor material in the first recess.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the semiconductor material in the bottom portion of the first recess comprises depositing undoped silicon in the bottom portion of the first recess.

### Claim 18 (depends on 17)

The method of claim 17, wherein after performing the third implantation process, a dopant concentration in the semiconductor material is in a range from 1×1020 atoms/cm3 to 1×1019 atoms/cm3.

### Claim 19 (depends on 17)

The method of claim 17, wherein after performing the third implantation process, the semiconductor material has a gradient-doped profile.

### Claim 20 (depends on 16)

The method of claim 16, wherein performing the first implantation process and the second implantation process comprises implanting arsenic (As), phosphorous (P), antimony (Sb), boron di-fluoride (BF2), or boron (B) into exposed portions of the multi-layer stack.