# US 12,218,195 B2 · Vertical semiconductor device in narrow slots within trench

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- Number: US 12,218,195 B2
- Document ID: US12218195B2
- Status: Granted
- Kind: B2
- Application number: 17/545,887
- Filed: 2021-12-08
- Published: 2023-06-08
- Granted: 2025-02-04
- Earliest claimed: 2021-12-08
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: H. Jim Fulford; Mark I. Gardner
- Web page: https://patentgrep.com/patent/US12218195B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/0167: {Manufacturing their channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/837: {comprising vertical IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed herein are related to a device including vertically placed semiconductor devices in a trench, and a method of fabricating the vertically placed semiconductor devices. In one aspect, a device includes a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall. The device may include two or more vertical slots separated by vertical nano sheets extending upwards from the floor within the trench. In one aspect, the semiconductor devices can be formed in the two or more vertical slots. For example, source/drain structures, gate structures, and additional source/drain structures of vertical transistors can be formed in the two or more vertical slots.

## Claims

### Claim 1

A method comprising:
forming a trench in a substrate, the trench defined by a first sidewall and a second sidewall facing each other along a first direction and a floor between one end of the first sidewall and one end of the second sidewall;
forming a dielectric layer on the floor;
forming a first epitaxial layer on the first sidewall along a second direction traversing the first direction;
forming a second epitaxial layer on the second sidewall along the second direction, the first epitaxial layer and the second epitaxial layer being a first type;
forming a third epitaxial layer on the first epitaxial layer along the second direction;
and
forming a fourth epitaxial layer on the second epitaxial layer along the second direction, the third epitaxial layer and the fourth epitaxial layer being a second type.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer extend from the dielectric layer along the second direction.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first epitaxial layer and the second epitaxial layer include SiGe and wherein the third epitaxial layer and the fourth epitaxial layer include Si, SiN+, or SiP+.

### Claim 4 (depends on 1)

The method of claim 1, wherein the trench is defined by a third sidewall and a fourth sidewall facing each other along a third direction orthogonal to the first direction and the second direction, the method further comprising:
forming a dielectric layer on the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall, prior to forming the first epitaxial layer and the second epitaxial layer; and
removing a first portion of the dielectric layer on the first sidewall, and a second portion of the dielectric layer on the second sidewall.

### Claim 5 (depends on 4)

The method of claim 4, wherein removing the first portion of the dielectric layer on the first sidewall, and the second portion of the dielectric layer on the second sidewall includes:
covering a third portion of the dielectric layer on the third sidewall, and a fourth portion of the dielectric layer on the fourth sidewall with a photoresist mask, while exposing the first portion and the second portion of the dielectric layer; and
etching the first portion and the second portion of the dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
removing portions of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer formed above a surface of the substrate.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
removing the first and second epitaxial layers.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a first source/drain structure between the first sidewall and the third epitaxial layer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
forming a gate dielectric region on the third epitaxial layer along the second direction, after forming the first source/drain structure.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a first spacer above the first source/drain structure along the second direction between the first sidewall and the third epitaxial layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a gate structure above the first spacer along the second direction between the first sidewall and the third epitaxial layer, the gate dielectric region formed between the gate structure and the third epitaxial layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a second spacer above the gate structure along the second direction between the first sidewall and the third epitaxial layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
removing an exposed portion of the gate dielectric region after depositing the second spacer; and
forming a second source/drain structure above the second spacer along the second direction between the first sidewall and the third epitaxial layer,
wherein a first end of the gate dielectric region directly contacts the first source/drain structure, and a second end of the gate dielectric region directly contacts the second source/drain structure.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
forming a first set of epitaxial layers of the first type and a second set of epitaxial layers of the second type between the first sidewall and the second sidewall, each of the second set of epitaxial layers of the second type interposed between two corresponding epitaxial layers of the first type; and
forming a third set of epitaxial layers of the first type and a fourth set of epitaxial layers of the second type between the first sidewall and the second sidewall, each of the fourth set of epitaxial layers of the second type interposed between two corresponding epitaxial layers of the first type.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
removing the first epitaxial layer, the second epitaxial layer, the first set of epitaxial layers, and the third set of epitaxial layers.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
forming a divider between i) one of the first set of epitaxial layers closest to the second sidewall and ii) one of the third set of epitaxial layers closest to the first sidewall.

### Claim 17

A device comprising:
a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall;
one or more epitaxial layers in the trench, each of the one or more epitaxial layers extending along a second direction traversing the first direction, wherein the first sidewall, the second sidewall, the floor of the trench, and the one or more epitaxial layers define two or more slots within the trench;
a first set of source/drain structures in the two or more slots above the floor of the trench along the second direction;
a second set of source/drain structures in the two or more slots above the first set of source/drain structures along the second direction; and
a set of gate structures in the two or more slots, each of the set of gate structures between a corresponding one of the first set of source/drain structures and a corresponding one of the second set of source/drain structures.

### Claim 18 (depends on 17)

The device of claim 17, further comprising:
gate dielectric regions, each of the gate dielectric regions on a portion of a corresponding epitaxial layer of the one or more epitaxial layers between a corresponding one of the first set of source/drain structures and a corresponding one of the second set of source/drain structures.

### Claim 19 (depends on 17)

The device of claim 17, further comprising:
a first set of spacers, each of the first set of spacers between a corresponding one of the first set of source/drain structures and a corresponding one of the set of gate structures; and
a second set of spacers, each of the second set of spacers between a corresponding one of the second set of source/drain structures and a corresponding one of the set of gate structures.

### Claim 20

A device comprising:
a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall;
a first epitaxial layer on the first sidewall along a second direction traversing the first direction;
a second epitaxial layer on the second sidewall along the second direction, the first epitaxial layer and the second epitaxial layer being a first type;
a third epitaxial layer on the first epitaxial layer along the second direction; and
a fourth epitaxial layer on the second epitaxial layer along the second direction, the third epitaxial layer and the fourth epitaxial layer being a second type.