# US 12,218,194 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,218,194 B2
- Document ID: US12218194B2
- Status: Granted
- Kind: B2
- Application number: 17/978,390
- Filed: 2022-11-01
- Published: 2023-02-23
- Granted: 2025-02-04
- Earliest claimed: 2020-09-14
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hae Jung Park
- Web page: https://patentgrep.com/patent/US12218194B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/076: {in via holes or trenches}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate including a plurality of active regions;
forming a plurality of bit line structures in which bit line contact plugs, bit lines, and bit line hard masks are stacked over the substrate;
forming an isolation layer filling a space between the bit line structures and having an opening exposing the active regions between the bit line structures;
forming a pad in a bottom portion of the opening;
forming plug liner over a sidewall of the opening and exposing the pad; and
forming a contact plug filling the opening over the pad,
wherein the upper surface of the pad is positioned at a lower level than the upper surface of the each bit line contact plug,
wherein the plug liner includes polysilicon.

### Claim 2 (depends on 1)

The method of claim 1, wherein in the forming of the pad in the bottom portion of the opening,
a selective epitaxial growth is performed from the active regions.

### Claim 3 (depends on 1)

The method of claim 1, wherein the pad includes a silicon-containing epitaxial layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming of the isolation layer filling the space between the bit line structures and having the opening exposing the active regions between the bit line structures includes:
forming a dielectric layer filling the space between the bit line structures;
forming a line mask intersecting with the bit line structure over the bit line structures and the dielectric layer;
etching a dielectric layer exposed between the line mask and the bit line structures;
forming an isolation layer filling a space between the etched dielectric layers;
removing the line mask; and
removing the dielectric layer between the isolation layers.

### Claim 5 (depends on 4)

The method of claim 4, wherein the isolation layer is a dielectric material having an etch selectivity with respect to the dielectric layer.

### Claim 6 (depends on 4)

The method of claim 4, wherein the line mask has an etch selectivity with respect to the bit line structures and the dielectric layer.

### Claim 7

A method for fabricating a semiconductor device, comprising:
providing a substrate including a plurality of active regions;
forming a plurality of bit line structures over an upper portion of the substrate;
forming an isolation layer having an opening that exposes the active regions between the bit line structures while filling the space between the bit line structures;
forming a pad in a bottom portion of the opening;
forming a first spacer over a sidewall of the opening and exposing the pad;
forming a plug liner covering in lower portion of the first spacer;
forming a first contact plug filling a portion of the opening over the pad;
forming a second spacer over the plug liner and covering an upper portion of the first spacer; and
forming a second contact plug filling a remaining portion of the opening over the first contact plug,
wherein the plug line includes polysilicon.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first spacer includes silicon oxide.

### Claim 9 (depends on 7)

The method of claim 7, wherein the second spacer includes silicon nitride.

### Claim 10 (depends on 7)

The method of claim 7, wherein the first and second contact plugs include polysilicon, a metal, a metal nitride, or a combination thereof.

### Claim 11 (depends on 7)

The method of claim 7, wherein in the forming of the pad in the bottom portion of the opening,
performing a selective epitaxial growth process from the active region.