# US 12,218,193 B2 · Integrated circuit device and method of forming the same

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- Number: US 12,218,193 B2
- Document ID: US12218193B2
- Status: Granted
- Kind: B2
- Application number: 17/528,251
- Filed: 2021-11-17
- Published: 2022-03-10
- Granted: 2025-02-04
- Earliest claimed: 2018-03-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jae-hyun Park; Kye-hyun Baek; Yong-ho Jeon; Cheol Kim; Sung-il Park; Yun-il Lee; Hyung-suk Lee
- Web page: https://patentgrep.com/patent/US12218193B2

## CPC

- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 84/0153: {using gate cut processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

## Claims

### Claim 1

An integrated circuit (IC) device, comprising:
fin patterns on a substrate along a first direction;
gate electrodes along a second direction perpendicular to the first direction;
source/drain regions on the fin patterns; and
an isolation region extending in the first direction between and in parallel with two adjacent fin patterns of the fin patterns, the isolation region separating at least one gate electrode of the gate electrodes into first and second gate electrodes,
wherein the isolation region includes a first portion between the first and second gate electrodes, and a second portion separated from the first portion along the first direction and having a non-overlapping relationship with the first and second gate electrodes, a thickness of the lowermost part of the first portion relative to a bottom of the substrate being larger than a thickness of the lowermost part of the second portion relative to a bottom of the substrate, and a lower part of the second portion having a decreasing width at a bottom thereof.

### Claim 2 (depends on 1)

The IC device as claimed in claim 1, further comprising:
a gate capping insulating layer on the gate electrodes, respectively; and
an inter-gate dielectric film between the gate electrodes, the inter-gate dielectric film including a material having a lower etch rate than a material of the gate capping insulating layer.

### Claim 3 (depends on 1)

The IC device as claimed in claim 1, further comprising a spacer surrounding sidewalls of the isolation region.

### Claim 4 (depends on 3)

The IC device as claimed in claim 3, wherein the spacer is only on upper sidewalls of the isolation region, a distance between the bottom of the substrate and a bottom of the spacer being larger than a distance between the bottom of the substrate and tops of source/drain regions on the fin patterns.

### Claim 5 (depends on 1)

The IC device as claimed in claim 1, wherein:
side surfaces of the first portion of the isolation region spaced apart from each other along the second direction face the first and second gate electrodes, respectively, and
side surfaces of the second portion of the isolation region spaced apart from each other along the second direction face a dielectric layer that covers the source/drain regions, respectively.

### Claim 6

An integrated circuit (IC) device, comprising:
a first region and a second region adjacent to each other along a first direction on a substrate;
fin patterns in each of the first region and the second region, the fin patterns extending along a second direction perpendicular to the first direction;
gate electrodes extending along the first direction and intersecting the fin patterns; and
an isolation region extending continuously in the second direction between two or more gate electrodes and between the first region and the second region, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate along the second direction.

### Claim 7 (depends on 6)

The IC device as claimed in claim 6, wherein:
the isolation region separates at least one gate electrode of the gate electrodes into first and second gate electrodes,
the isolation region includes a first portion between the first and second gate electrodes, and a second portion having a non-overlapping relationship with the first and second gate electrodes, and
the first portion and the second portion are integral with each other in a single, seamless structure, top surfaces of the first portion and the second portion being level with each other.

### Claim 8 (depends on 6)

The IC device as claimed in claim 6, wherein:
the isolation region separates at least one gate electrode of the gate electrodes into first and second gate electrodes,
the isolation region includes a first portion between the first and second gate electrodes, and a second portion having a non-overlapping relationship with the first and second gate electrodes, and
a distance between the bottom of the substrate and a bottom of the first portion is smaller than a distance between the bottom of the substrate and a bottommost surface of each of the first and second gate electrodes.

### Claim 9 (depends on 6)

The IC device as claimed in claim 6, wherein:
the isolation region includes a first portion and a second portion, the first portion having a prismatic shape, and the second portion including protrusions extending from the prismatic shape toward the substrate, and
the protrusions are spaced apart from each other along the second direction.

### Claim 10 (depends on 6)

The IC device as claimed in claim 6, wherein the isolation region has a non-overlapping relationship with the gate electrodes in a top view.

### Claim 11 (depends on 6)

The IC device as claimed in claim 6, wherein the isolation region is a continuous insulating structure, an entirety of the isolation region being between two adjacent fin patterns of the fin patterns.

### Claim 12 (depends on 6)

The IC device as claimed in claim 6, further comprising:
a gate capping insulating layer on the gate electrodes, respectively; and
an inter-gate dielectric film between the gate electrodes, the inter-gate dielectric film including a material different from a material of the gate capping insulating layer.

### Claim 13 (depends on 6)

The IC device as claimed in claim 6, further comprising a spacer surrounding sidewalls of the isolation region.

### Claim 14 (depends on 13)

The IC device as claimed in claim 13, wherein the spacer is only on upper sidewalls of the isolation region, a distance between the bottom of the substrate and a bottom of the spacer is larger than a distance between the bottom of the substrate and tops of source/drain regions on the fin patterns.

### Claim 15 (depends on 6)

The IC device as claimed in claim 6, wherein:
the isolation region separates at least one gate electrode of the gate electrodes into first and second gate electrodes, and
side surfaces of the isolation region spaced apart from each other along the first direction face the first and second gate electrodes, respectively.

### Claim 16

An integrated circuit (IC) device, comprising:
a first region and a second region adjacent to each other along a first direction on a substrate;
fin patterns in each of the first region and the second region, the fin patterns extending along a second direction perpendicular to the first direction;
gate electrodes extending along the first direction and intersecting the fin patterns; and
an isolation region extending continuously in the second direction between two or more gate electrodes and between the first region and the second region, an entirety of a width of the isolation region along the first direction being between two of the fin patterns that are directly adjacent to each other along the first direction,
wherein a bottom of the isolation region extending in the second direction has a non-uniform height relative to a bottom of the substrate along the second direction.

### Claim 17 (depends on 16)

The IC device as claimed in claim 16, wherein:
the isolation region separates at least one gate electrode of the gate electrodes into first and second gate electrodes,
the isolation region includes a first portion between the first and second gate electrodes, and a second portion having a non-overlapping relationship with the first and second gate electrodes, and
the first portion and the second portion are integral with each other in a single, seamless structure, top surfaces of the first portion and the second portion being level with each other.

### Claim 18 (depends on 16)

The IC device as claimed in claim 16, wherein a lower part of the isolation region has a smaller width as the lower part approaches the substrate.

### Claim 19 (depends on 16)

The IC device as claimed in claim 16, wherein:
the isolation region separates at least one gate electrode of the gate electrodes into first and second gate electrodes, and
side surfaces of the isolation region spaced apart from each other along the first direction face the first and second gate electrodes, respectively.