# US 12,218,190 B2 · False collectors and guard rings for semiconductor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,190 B2
- Document ID: US12218190B2
- Status: Granted
- Kind: B2
- Application number: 17/731,510
- Filed: 2022-04-28
- Published: 2023-10-05
- Granted: 2025-02-04
- Earliest claimed: 2022-03-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Alexei Sadovnikov; Guruvayurappan S. Mathur
- Web page: https://patentgrep.com/patent/US12218190B2

## CPC

- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/60: Lateral BJTs
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/30: Isolation regions comprising PN junctions
- H10D 30/655: {having edge termination structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

## Claims

### Claim 1

A method of manufacturing an integrated circuit, the method comprising:
forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material,
the first false collector region being located laterally on a first side of a base region, the base region formed within the epitaxial layer and having a second conductivity type,
the second false collector region being located laterally on a second side of the base region, the second side being opposite the first side of the base region, and
the base region being a base of a parasitic bipolar junction in an isolation region of a semiconductor device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming first and second guard regions of the second conductivity type adjacent to the surface of the epitaxial layer, wherein:
the first guard region is located laterally from the first false collector region so the first false collector region is located between the first guard region and the base region; and
the second guard region is located laterally from the second false collector region so the second false collector region is located between the second guard region and the base region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first conductivity type comprises arsenic or phosphorus dopant, and the second conductivity type comprises boron dopant.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first and second false collector regions have a dopant concentration of between about 1×1019 ions/cm3 and about 1×1020 ions/cm3.

### Claim 6 (depends on 1)

The method of claim 1, wherein the epitaxial layer is of the second conductivity type.

### Claim 7 (depends on 1)

The method of claim 1, wherein prior to forming the epitaxial layer, the method further comprises:
forming a deep trench isolation sidewall and doping the deep trench isolation sidewall to be the first conductivity type so the deep trench isolation sidewall forms an emitter of the parasitic bipolar junction.

### Claim 8 (depends on 7)

The method of claim 7, further forming a collector region of the first conductivity type adjacent to the surface of the epitaxial layer, the collector region being a collector of the parasitic bipolar junction.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming first and second field oxide regions in the epitaxial layer, wherein:
the first field oxide region is located between the first false collector region and a collector region of the parasitic bipolar junction; and
the second field oxide region is located between the second false collector region and an emitter region of the parasitic bipolar junction.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
implanting dopant of the second conductivity type into the epitaxial layer to form a buried layer; and
connecting the buried layer to the base region.

### Claim 11 (depends on 1)

The method of claim 1, wherein the isolation region at least partially surrounds the semiconductor device.

### Claim 12 (depends on 1)

The method of claim 1, wherein the semiconductor device includes a lateral-diffused metal-oxide-semiconductor (LDMOS) transistor, a diode, or a bipolar transistor.

### Claim 13

A method of fabricating an integrated circuit, comprising:
implanting dopant of a first conductivity type into a semiconductor substrate to form a first buried layer;
forming an epitaxial layer of a second conductivity type on the semiconductor substrate over the first buried layer, the second conductivity type being opposite the first conductivity type;
forming a deep trench isolation sidewall of the first conductivity type over the semiconductor substrate;
forming an oxide layer over the epitaxial layer;
implanting dopant of the second conductivity type into the epitaxial layer to form a second buried layer;
implanting dopant of the second conductivity type into the epitaxial layer above the second buried layer to form a deep region that is adjacent to the second buried layer and between the oxide layer and the second buried layer;
implanting dopant of the first conductivity type into the epitaxial layer above the second buried layer to form a collector region, the collector region located laterally from the deep region and extending from a surface of the epitaxial layer to terminate at a location spaced from the second buried layer;
implanting dopant of the second conductivity type into the epitaxial layer above the second buried layer to form first, second, and third shallow well regions, the third shallow well region located laterally between the first and second shallow well regions, the third shallow well region formed over the deep region;
implanting dopant of the first conductivity type into the epitaxial layer to form first and second false collector regions adjacent to the surface of the epitaxial layer, the first false collector region being located laterally between the first shallow well region and the third shallow well region, and the second false collector region being located laterally between the third shallow well region and the second shallow well region; and
implanting dopant of the second conductivity type into the epitaxial layer to form a base region extending between the third shallow well region and the surface of the epitaxial layer, the base region forming a base of a bipolar junction of a lateral isolation region, the collector region forming a collector of the bipolar junction, and the deep trench isolation sidewall forming an emitter of the bipolar junction.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first and second false collector regions are doped with arsenic or phosphorus.

### Claim 15 (depends on 14)

The method of claim 14, wherein the dopant of the first conductivity type in the first and second false collector regions has a concentration of between about 1×1019 ions/cm3 and about 1×1020 ions/cm3.

### Claim 16 (depends on 13)

The method of claim 13, wherein the first and second shallow well regions are doped with boron.

### Claim 17 (depends on 16)

The method of claim 16, wherein the dopant of the second conductivity type in the first and second shallow well regions has a concentration of between about 1×1016 ions/cm3 and about 1×1018 ions/cm3.

### Claim 18

A method, comprising:
forming a trench isolation sidewall of a first conductivity type in a semiconductor layer of a second conductivity type, wherein the trench isolation sidewall forms an emitter of a bipolar junction of an isolation region;
implanting dopant of the first conductivity type into the semiconductor layer to form a collector region located laterally away from the trench isolation sidewall, wherein the collector region forms a collector of the bipolar junction;
implanting dopant of the first conductivity type into the semiconductor layer to form first and second false collector regions, the first and second false collector regions being separated from each other and located laterally between the collector region and the trench isolation sidewall, wherein the first false collector region is located laterally closer to the collector region than the second false collector region; and
implanting dopant of the second conductivity type into the semiconductor layer to form a base region that forms a base of the bipolar junction, wherein the base region is located between the first and second false collector regions.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
implanting dopant of the second conductivity type into the semiconductor layer to form first and second guard ring regions, wherein:
the first guard ring region is located between the collector region and the first false collector region; and
the second guard ring region is located between the second false collector region and the trench isolation sidewall.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
forming first and second field oxide regions in the semiconductor layer, wherein:
the first field oxide region is located between the collector region and the first false collector region; and
the second field oxide region is located between the second false collector region and the trench isolation sidewall.

### Claim 21 (depends on 18)

The method of claim 18, further comprising:
implanting dopant of the second conductivity type into the semiconductor layer to form a buried layer; and
connecting the buried layer to the base region.

### Claim 22 (depends on 18)

The method of claim 18, wherein the isolation region at least partially surrounds a semiconductor device.

### Claim 23 (depends on 22)

The method of claim 22, wherein the semiconductor device includes a lateral-diffused metal-oxide-semiconductor (LDMOS) transistor, a diode, or a bipolar transistor.