# US 12,218,189 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 12,218,189 B2
- Document ID: US12218189B2
- Status: Granted
- Kind: B2
- Application number: 18/518,797
- Filed: 2023-11-24
- Published: 2024-03-14
- Granted: 2025-02-04
- Earliest claimed: 2021-05-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsin-Fu Lin; Tsung-Hao Yeh; Chih-Wei Hung
- Web page: https://patentgrep.com/patent/US12218189B2

## CPC

- H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.

## Claims

### Claim 1

A method for manufacturing a semiconductor device comprising:
forming a trench in a semiconductor layer;
forming a dielectric film in the trench;
forming an anti-type doping layer beneath the dielectric film;
forming a drift region in the semiconductor layer in a way that the anti-type doping layer is located between the drift region and the dielectric film, the drift region having a first conductivity type opposite to a second conductivity type of the anti-type doping layer; and
forming a drain area within a portion of the drift region, the drain area having the first type conductivity and having a doping concentration higher than a doping concentration of the drift region,
the anti-type doping layer being disposed to entirely separate the drift region and the drain area from the dielectric film.

### Claim 2 (depends on 1)

The method of claim 1, wherein the semiconductor layer includes crystalline silicon, polycrystalline silicon, or a combination thereof.

### Claim 3 (depends on 1)

The method of claim 1, wherein formation of the dielectric film includes
forming a dielectric layer on the semiconductor layer to fill the trench,
removing an excess of the dielectric layer to expose the semiconductor layer so as to form the dielectric layer into the dielectric film.

### Claim 4 (depends on 1)

The method of claim 1, wherein formation of the anti-type doping layer includes
forming a patterned mask on the semiconductor layer to expose the dielectric film and a surrounding surface of the semiconductor layer around the dielectric film,
doping a region beneath the dielectric film through the patterned mask using an ion implantation process so as to form the anti-type doping layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the anti-type doping layer has a thickness ranging from 50 Å to 200 Å.

### Claim 6 (depends on 1)

The method of claim 1, wherein the anti-type doping layer has a doping concentration higher than the doping concentration of the drift region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the anti-type doping layer has a doping concentration lower than the doping concentration of the drain area.

### Claim 8 (depends on 7)

The method of claim 7, wherein the doping concentration of the anti-type doping layer is higher than the doping concentration of the drain area by two orders of magnitude.

### Claim 9

A method for manufacturing a semiconductor device comprising:
forming a trench in a semiconductor layer;
forming a dielectric film in the trench;
forming an anti-type doping layer beneath the dielectric film;
forming a drift region in the semiconductor layer in a way that the anti-type doping layer is located between the drift region and the dielectric film, the drift region having a first conductivity type opposite to a second conductivity type of the anti-type doping layer;
forming a drain area within a portion of the drift region, the drain area having the first type conductivity and having a doping concentration higher than a doping concentration of the drift region; and
forming a source area in the semiconductor layer in a way that the dielectric film is located between the source area and the drain area, the source area having the first conductivity type,
the anti-type doping layer being disposed to entirely separate the drift region and the drain area from the dielectric film.

### Claim 10 (depends on 9)

The method of claim 9, wherein the semiconductor layer includes crystalline silicon, polycrystalline silicon, or a combination thereof.

### Claim 11 (depends on 9)

The method of claim 9, wherein formation of the dielectric film includes
forming a dielectric layer on the semiconductor layer to fill the trench,
removing an excess of the dielectric layer to expose the semiconductor layer so as to form the dielectric layer into the dielectric film.

### Claim 12 (depends on 9)

The method of claim 9, wherein formation of the anti-type doping layer includes
forming a patterned mask on the semiconductor layer to expose the dielectric film and a surrounding surface of the semiconductor layer around the dielectric film,
doping a region beneath the dielectric film through the patterned mask using an ion implantation process so as to form the anti-type doping layer.

### Claim 13 (depends on 9)

The method of claim 9, wherein the anti-type doping layer has a thickness ranging from 50 Å to 200 Å.

### Claim 14 (depends on 1)

The method of claim 1, wherein the anti-type doping layer has a doping concentration higher than the doping concentration of the drift region.

### Claim 15 (depends on 9)

The method of claim 9, wherein the anti-type doping layer has a doping concentration lower than the doping concentration of the drain area.

### Claim 16 (depends on 15)

The method of claim 15, wherein the doping concentration of the anti-type doping layer is higher than the doping concentration of the drain area by two orders of magnitude.

### Claim 17

A method for manufacturing a semiconductor device comprising:
forming a trench in a semiconductor layer;
forming a dielectric film in the trench;
forming an anti-type doping layer beneath the dielectric film;
forming a drift region in the semiconductor layer in a way that the anti-type doping layer is located between the drift region and the dielectric film, the drift region having a first conductivity type opposite to a second conductivity type of the anti-type doping layer;
forming a drain area within a portion of the drift region, the drain area having the first type conductivity and having a doping concentration higher than a doping concentration of the drift region;
forming a source area in the semiconductor layer in a way that the dielectric film is located between the source area and the drain area, the source area having the first conductivity type; and
forming a well region in the semiconductor layer in a way that the well region is located to separate the source area from the drift region, the well region having the second type conductivity,
the anti-type doping layer being disposed to entirely separate the drift region and the drain area from the dielectric film.

### Claim 18 (depends on 17)

The method of claim 17, further comprising
forming a gate structure over a portion of the dielectric film, a portion of the anti-type doping layer, a portion of the drift region, and a portion of the well region.

### Claim 19 (depends on 18)

The method of claim 18, wherein the gate structure includes a gate electrode and a gate dielectric located beneath the gate electrode.

### Claim 20 (depends on 17)

The method of claim 17, wherein the gate structure further includes two spacers formed at two opposite sides of a stack of the gate electrode and the gate dielectric.