# US 12,218,188 B2 · Deep trench intersections > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,188 B2 - Document ID: US12218188B2 - Status: Granted - Kind: B2 - Application number: 17/380,060 - Filed: 2021-07-20 - Published: 2021-11-11 - Granted: 2025-02-04 - Earliest claimed: 2020-02-10 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Binghua Hu; Ye Shao; John K Arch - Web page: https://patentgrep.com/patent/US12218188B2 ## CPC - H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10P 50/691: {for Group IV materials or Group III-V materials} - H10P 52/403: {of conductive or resistive materials} - H10P 95/062: {involving a dielectric removal step} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments. ## Claims ### Claim 1 A semiconductor device, comprising: a deep trench structure in a semiconductor substrate, the deep trench structure including: a first linear trench having a first width; a second linear trench having a second width; a third linear trench having a third width; a fourth linear trench having a fourth width; a trench intersection, wherein the first, second, third and fourth linear trenches extend into the trench intersection, the trench intersection including: a first connector trench connecting the first linear trench to the second linear trench; a second connector trench connecting the second linear trench to the third linear trench; a third connector trench connecting the third linear trench to the fourth linear trench; and a fourth connector trench connecting the fourth linear trench to the first linear trench; and a substrate pillar including a material of the semiconductor substrate, wherein: the substrate pillar is laterally surrounded by the trench intersection; the first connector trench follows a first arced path with a first inner radius that is 1.4 to 2.0 times a minimum of the first and second widths; the second connector trench follows a second arced path with a second inner radius that is 1.4 to 2.0 times a minimum of the second and third widths; the third connector trench follows a third arced path with a third inner radius that is 1.4 to 2.0 times a minimum of the third and fourth widths; and the fourth connector trench follows a fourth arced path with a fourth inner radius that is 1.4 to 2.0 times a minimum of the fourth and first widths, such that the substrate pillar has an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first, second, third, and fourth widths. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the substrate pillar abuts the first, second, third, and fourth connector trenches. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein: the first connector trench has a first connector width between a minimum of the first and second widths and a maximum of the first and second widths; the second connector trench has a second connector width between a minimum of the second and third widths and a maximum of the second and third widths; the third connector trench has a third connector width between a minimum of the third and fourth widths and a maximum of the third and fourth widths; and the fourth connector trench has a fourth connector width between a minimum of the fourth and first widths and a maximum of the fourth and first widths. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein: the first linear trench is perpendicular to the second linear trench and to the fourth linear trench; the first linear trench is parallel to, and aligned with, the third linear trench; and the second linear trench is aligned with the fourth linear trench. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first, second, third, and fourth widths are equal. ### Claim 6 A method, comprising: forming a deep trench in a semiconductor substrate having a top surface, the deep trench extending into the semiconductor substrate from the top surface; and filling the deep trench with a trench filler material to form a deep trench structure, the deep trench structure including: a first linear trench having a first width; a second linear trench having a second width; a third linear trench having a third width; a fourth linear trench having a fourth width: a first connector trench connecting the first linear trench to the second linear trench; a second connector trench connecting the second linear trench to the third linear trench; a third connector trench connecting the third linear trench to the fourth linear trench; and a fourth connector trench connecting the fourth linear trench to the first linear trench, wherein: the first, second, third connector trenches laterally surround a substrate pillar that includes a material of the semiconductor substrate, the first connector trench follows a first arced path with a first inner radius that is 1.4 to 2.0 times a minimum of the first and second widths; the second connector trench follows a second arced path with a second inner radius that is 1.4 to 2.0 times a minimum of the second and third widths; the third connector trench follows a third arced path with a third inner radius that is 1.4 to 2.0 times a minimum of the third and fourth widths; and the fourth connector trench follows a fourth arced path with a fourth inner radius that is 1.4 to 2.0 times a minimum of the fourth and first widths, such that the substrate pillar has an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first, second, third, and fourth widths. ### Claim 7 (depends on 6) The method of claim 6, wherein the substrate pillar abuts the first, second, third and fourth connector trenches. ### Claim 8 (depends on 6) The method of claim 6, further comprising: forming a dielectric liner in the deep trench prior to filling the deep trench, the trench filler material being formed on the dielectric liner. ### Claim 9 (depends on 6) The method of claim 6, wherein filling the deep trench with the trench filler material to form the deep trench structure includes: filling the deep trench with the trench filler material, wherein the trench filler material extends over the top surface of the semiconductor substrate; and removing the trench filler material from over the top surface of the semiconductor substrate. ### Claim 10 (depends on 9) The method of claim 9, wherein removing the trench filler material from over the top surface of the semiconductor substrate includes a chemical mechanical polish (CMP) process. ### Claim 11 (depends on 6) The method of claim 6, wherein the trench filler material includes polycrystalline silicon. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the deep trench structure includes a trench filler material on a dielectric liner disposed on an inner surface of a trench formed in the semiconductor substrate. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the dielectric liner includes an opening in a portion of a bottom of the trench such that the trench filler material directly touches the semiconductor substrate through the opening. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein the deep trench structure includes a trench filler material disposed directly on an inner surface of a trench formed in the semiconductor substrate. ### Claim 15 (depends on 1) The semiconductor device of claim 1, wherein: the first and third widths have a first dimension; and the second and fourth widths have a second dimension different than the first dimension. ### Claim 16 (depends on 6) The method of claim 6, wherein: the first connector trench has a first connector width between a minimum of the first and second widths and a maximum of the first and second widths; the second connector trench has a second connector width between a minimum of the second and third widths and a maximum of the second and third widths; the third connector trench has a third connector width between a minimum of the third and fourth widths and a maximum of the third and fourth widths; and the fourth connector trench has a fourth connector width between a minimum of the fourth and first widths and a maximum of the fourth and first widths. ### Claim 17 A semiconductor device, comprising: a deep trench structure in a semiconductor substrate, the deep trench structure including: a first linear trench having a first width; a second linear trench having a second width; a third linear trench having a third width; a fourth linear trench having a fourth width: a trench intersection, wherein the first, second, third and fourth linear trenches extend into the trench intersection, the trench intersection including: a first connector trench connecting the first linear trench to the second linear trench, wherein the distance across the first connector trench to a substrate pillar has a fifth width, wherein the fifth width is greater than the lesser of the first width and the second width; a second connector trench connecting the second linear trench to the third linear trench, wherein the distance across the second connector trench to the substrate pillar has a sixth width, wherein the sixth width is greater than the lesser of the second width and the third width; a third connector trench connecting the third linear trench to the fourth linear trench, wherein the distance across the first connector trench to the substrate pillar has a seventh width, wherein the seventh width is greater than the lesser of the third width and the fourth width; and a fourth connector trench connecting the fourth linear trench to the first linear trench, wherein the distance across the first connector trench to the substrate pillar has an eighth width, wherein the eighth width is greater than the lesser of the fourth width and the first width; and the substrate pillar including a material of the semiconductor substrate, wherein: the substrate pillar is laterally surrounded by the trench intersection; the first connector trench follows a first arced path with a first inner radius that is 1.4 to 2.0 times a minimum of the first and second widths; the second connector trench follows a second arced path with a second inner radius that is 1.4 to 2.0 times a minimum of the second and third widths; the third connector trench follows a third arced path with a third inner radius that is 1.4 to 2.0 times a minimum of the third and fourth widths; and the fourth connector trench follows a fourth arced path with a fourth inner radius that is 1.4 to 2.0 times a minimum of the fourth and first widths, such that the substrate pillar has an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first, second, third, and fourth widths. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein: wherein the fifth width is less than the greater of the first width and the second width; wherein the sixth width is less than the greater of the second width and the third width; wherein the seventh width is less than the greater of the third width and the fourth width; and wherein the eighth width is less than the greater of the fourth width and the first width. ### Claim 19 (depends on 17) The semiconductor device of claim 17, wherein the substrate pillar abuts the first, second, third, and fourth connector trenches. ### Claim 20 (depends on 17) The semiconductor device of claim 17, wherein the first, second, third, and fourth widths are different.