# US 12,218,160 B2 · Pixel sensor including a layer stack to reduce and/or block the effects of plasma processing and etching on the pixel sensor

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- Number: US 12,218,160 B2
- Document ID: US12218160B2
- Status: Granted
- Kind: B2
- Application number: 17/249,788
- Filed: 2021-03-12
- Published: 2022-09-15
- Granted: 2025-02-04
- Earliest claimed: 2021-03-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei-Lin Chen; Ching-Chung Su; Chun-Hao Chou; Kuo-Cheng Lee
- Web page: https://patentgrep.com/patent/US12218160B2

## CPC

- H10F 39/804: {Containers or encapsulations}
- H10F 39/024: {of coatings or optical elements}
- H10F 39/182: {Colour image sensors}
- H10F 39/8053: {Colour filters}
- H10F 39/8063: {Microlenses}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.

## Claims

### Claim 1

A method, comprising:
forming a plurality of photodiodes in a substrate of a pixel array,
wherein each of the plurality of photodiodes is associated with a respective pixel sensor included in the pixel array;
forming a first oxide layer over the plurality of photodiodes;
forming a silicon nitride layer directly on the first oxide layer,
wherein a band gap of the silicon nitride layer is lower than a band gap of the first oxide layer;
forming a second oxide layer directly on the silicon nitride layer;
forming a grid structure over the second oxide layer;
forming a passivation liner over a top layer of the grid structure, on sidewalls of the grid structure, and on a portion of the second oxide layer;
removing a first portion of the passivation liner from the second oxide layer;
forming a plurality of color filter regions in between portions of the passivation liner on the sidewalls of the grid structure and directly on a surface of the second oxide layer; and
forming a micro-lens layer over a second portion of the passivation liner and over the plurality of color filter regions,
wherein the second portion of the passivation liner is over an entire portion of the top layer of the grid structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the grid structure comprises:
forming a plurality of layers over the second oxide layer; and
etching through the plurality of layers and into the portion of the second oxide layer to form openings for the grid structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein the grid structure comprises a composite metal grid (CMG) structure.

### Claim 4 (depends on 1)

The method of claim 1, wherein the grid structure comprises a color filter in a box (CIAB) structure.

### Claim 5

A system, comprising:
one or more semiconductor processing tools configured to:
form a plurality of photodiodes in a substrate of a pixel array,
wherein each of the plurality of photodiodes s associated with a respective pixel sensor included in the pixel array;
form a first oxide layer over the plurality of photodiodes;
form a silicon nitride layer directly on the first oxide layer,
wherein a band gap of the silicon nitride layer is lower than a band gap of the first oxide layer;
form a second oxide layer directly on the silicon nitride layer;
form a grid structure over the second oxide layer;
form a passivation liner over a top layer of the grid structure, on sidewalls of the grid structure, and on a portion of the second oxide layer;
remove a first portion of the passivation liner from the second oxide layer;
form a plurality of color filter regions in between portions of the passivation liner on the sidewalls of the grid structure and directly on a surface of the second oxide layer; and
form a micro-lens layer over a second portion of the passivation liner and over the plurality of color filter regions,
wherein the second portion of the passivation liner is over an entire portion of the top layer of the grid structure.

### Claim 6 (depends on 5)

The system of claim 5, wherein the one or more semiconductor processing tools, to form the grid structure, are configured to:
form a plurality of layers over the second oxide layer; and
etch through the plurality of layers and into the portion of the second oxide layer to form openings for the grid structure.

### Claim 7 (depends on 5)

The system of claim 5, wherein the grid structure comprises a composite metal grid (CMG) structure.

### Claim 8 (depends on 5)

The system of claim 5, wherein the grid structure comprises a color filter in a box (CIAB) structure.

### Claim 9 (depends on 5)

The system of claim 5, wherein the band gap of the silicon oxide layer is less than 8.8 electron-volts.

### Claim 10 (depends on 2)

The method of claim 2, wherein the surface of the second oxide layer is formed based on the portion of the second oxide layer being etched.

### Claim 11 (depends on 6)

The system of claim 6, wherein the surface of the second oxide layer is formed based on the portion of the second oxide layer being etched.

### Claim 12

A method, comprising:
forming a plurality of photodiodes between an isolation structure and in a substrate of a pixel array,
wherein each of the plurality of photodiodes is associated with a respective pixel sensor included in the pixel array;
forming a layer stack over the plurality of photodiodes and the isolation structure, wherein the layer stack comprises a first layer, a second layer directly on the first layer, and a third layer directly on the second layer, wherein the second layer comprises silicon nitride;
forming a grid structure over a portion of the layer stack that is over the isolation structure,
wherein the grid structure includes a tungsten layer;
forming a passivation liner on a top of the grid structure, on sidewalls of the grid structure, and on a portion of the layer stack;
removing a first portion of the passivation liner from the layer stack;
forming a plurality of color filter regions in between portions of the passivation liner on the sidewalls of the grid structure and directly on a surface of the layer stack; and
forming a micro-lens layer over a second portion of the passivation liner and over the plurality of color filter regions,
wherein the second portion of the passivation liner is over an entire portion of the grid structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the grid structure further includes a titanium nitride (TiN) layer, and
wherein forming the grid structure comprises:
forming the tungsten layer over the TiN layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the grid structure further comprises:
etching through the TiN layer and the tungsten layer and into the portion of the layer stack to form openings for the grid structure.

### Claim 15 (depends on 12)

The method of claim 12, wherein forming the grid structure comprises:
forming an oxide layer over the tungsten layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the grid structure further comprises:
forming a hard mask layer over the oxide layer.

### Claim 17 (depends on 12)

The method of claim 12, wherein forming the grid structure comprises:
forming a titanium nitride (TiN) layer;
forming the tungsten layer over the TiN layer;
forming an oxide layer over the tungsten layer; and
forming a hard mask layer over the oxide layer.

### Claim 18 (depends on 1)

The method of claim 1, wherein the plurality of photodiodes are formed in an upper portion of that substrate that is adjacent to the first oxide layer.

### Claim 19 (depends on 1)

The method of claim 1, further comprising:
forming a high dielectric constant (high-k) dielectric layer on the substrate,
wherein the first oxide layer is formed on the high-k dielectric layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein at least one of:
the oxide layer has a thickness of approximately 2900 angstroms to approximately 3700 angstroms, or
the hard mask layer includes a silicon nitride (SixNy) or a silicon oxynitride (SiON).