# US 12,218,156 B2 · Display device having power line electrically connected to electrode layers located above and below transistor

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- Number: US 12,218,156 B2
- Document ID: US12218156B2
- Status: Granted
- Kind: B2
- Application number: 18/388,594
- Filed: 2023-11-10
- Published: 2024-03-07
- Granted: 2025-02-04
- Earliest claimed: 2018-06-29
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Youngin Hwang; Elly Gil; Sungho Kim; Eungtaek Kim; Yongho Yang; Seongmin Wang; Jina Lee; Joohyeon Jo; Seongbaik Chu
- Web page: https://patentgrep.com/patent/US12218156B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G09G 3/3225: using an active matrix
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1216: {the pixel elements being capacitors}
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0852: being a dynamic memory with more than one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0242: Compensation of deficiencies in the appearance of colours
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display device includes: a first electrode layer; a semiconductor layer including a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged adjacent to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.

## Claims

### Claim 1

A display device comprising:
a bottom metal layer;
a semiconductor layer disposed on the bottom metal layer;
a first electrode layer disposed on the semiconductor layer;
a second electrode layer disposed on the first electrode layer and overlapping the first electrode layer;
a power line disposed on the second electrode layer and electrically connected to the bottom metal layer and the second electrode layer; and
a light-emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode,
wherein a first end of the semiconductor layer is electrically connected to the power line and a second end of the semiconductor layer is electrically connected to the pixel electrode,
wherein the semiconductor layer comprises a source area, a drain area, and a channel area between the source area and the drain area,
wherein each of the bottom metal layer, the first electrode layer, the second electrode layer, and the power line overlaps the channel area of the semiconductor layer, and
wherein the channel area of the semiconductor layer is located between a connected part of the power line and the first end of the semiconductor layer and a connected part of the second end of the semiconductor layer and the pixel electrode.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the second electrode layer is between the first electrode layer and the power line and is electrically insulated from the first electrode layer.

### Claim 3 (depends on 1)

The display device of claim 1, wherein the semiconductor layer comprises polysilicon.

### Claim 4 (depends on 1)

The display device of claim 1, wherein the power line is configured to receive a substantially constant voltage.

### Claim 5 (depends on 1)

The display device of claim 1, wherein the channel region of the semiconductor layer is curved.

### Claim 6 (depends on 1)

The display device of claim 1, further comprising:
a first insulating layer disposed between the bottom metal layer and the semiconductor layer;
a second insulating layer disposed between the semiconductor layer and the first electrode layer;
a third insulating layer disposed between the first electrode layer and the second electrode layer; and
a fourth insulating layer disposed between the second electrode layer and the power line.

### Claim 7

A display device comprising:
a substrate;
a driving transistor disposed on the substrate, the driving transistor comprising a semiconductor layer and a gate electrode;
a power line disposed on the driving transistor and electrically connected to the driving transistor;
a bottom metal layer arranged between the substrate and the semiconductor layer; and
an electrode layer overlapping the gate electrode of the driving transistor and electrically connected to the power line; and
a light-emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode,
wherein the semiconductor layer overlaps the bottom metal layer,
wherein the power line and the bottom metal layer are configured to receive a same voltage,
wherein a first end of the semiconductor layer is electrically connected to the power line and a second end of the semiconductor layer is electrically connected to the pixel electrode,
wherein the semiconductor layer comprises a source area, a drain area, and a channel area between the source area and the drain area,
wherein each of the bottom metal layer, the gate electrode of the driving transistor, the electrode layer, and the power line overlaps the channel area of the semiconductor layer, and
wherein the channel area of the semiconductor layer is located between a connected part of the power line and the first end of the semiconductor layer and a connected part of the second end of the semiconductor layer and the pixel electrode.

### Claim 8 (depends on 7)

The display device of claim 7, wherein the semiconductor layer comprises polysilicon.

### Claim 9 (depends on 7)

The display device of claim 7, further comprising:
a first insulating layer disposed between the bottom metal layer and the semiconductor layer;
a second insulating layer disposed between the semiconductor layer and a first electrode layer;
a third insulating layer disposed between the first electrode layer and a second electrode layer; and
a fourth insulating layer disposed between the second electrode layer and the power line.

### Claim 10 (depends on 7)

The display device of claim 7, further comprising:
a buffer layer disposed between the substrate and the bottom metal layer.

### Claim 11 (depends on 7)

The display device of claim 7, wherein the substrate comprises an organic layer and an inorganic layer.

### Claim 12

A display device comprising:
a substrate;
a bottom metal layer on the substrate;
a first transistor overlapping the bottom metal layer and comprising a first semiconductor layer and a first gate electrode;
an electrode layer overlapping the first gate electrode of the first transistor;
a power line disposed on the first transistor and electrically connected to the electrode layer;
a second transistor comprising a second semiconductor layer and a second gate electrode;
a connection electrode electrically connecting the first gate electrode of the first transistor and a first end of the second semiconductor layer; and
a light-emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode,
wherein a first end of the first semiconductor layer is electrically connected to the power line and a second end of the first semiconductor layer is electrically connected to the pixel electrode, and
wherein a second end of the second semiconductor layer is electrically connected to the second end of the first semiconductor layer.

### Claim 13 (depends on 12)

The display device of claim 12,
wherein the first semiconductor layer comprises a source area, a drain area, and a channel area between the source area and the drain area, and
wherein each of the bottom metal layer, the first gate electrode, the electrode layer, and the power line overlaps the channel area of the first semiconductor layer.

### Claim 14 (depends on 12)

The display device of claim 12, wherein the electrode layer is electrically insulated from the first gate electrode of the first transistor.

### Claim 15 (depends on 12)

The display device of claim 12, wherein the first semiconductor layer comprises polysilicon.

### Claim 16 (depends on 12)

The display device of claim 12, wherein the channel region of the semiconductor layer is curved.

### Claim 17 (depends on 12)

The display device of claim 12, further comprising:
a buffer layer disposed between the substrate and the bottom metal layer.

### Claim 18 (depends on 12)

The display device of claim 12, wherein the substrate comprises an organic layer and an inorganic layer.

### Claim 19 (depends on 12)

The display device of claim 12, further comprising:
a data line disposed on a same layer as the power line.

### Claim 20 (depends on 12)

The display device of claim 12, wherein a part of the power line and a part of the data line overlap the electrode layer.