# US 12,218,155 B2 · Semiconductor device with multiple zero differential transconductance and method of manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,155 B2 - Document ID: US12218155B2 - Status: Granted - Kind: B2 - Application number: 17/575,732 - Filed: 2022-01-14 - Published: 2022-07-14 - Granted: 2025-02-04 - Earliest claimed: 2021-01-14 - Assignees: Research & Business Foundation Sungkyunkwan University - Applicants: Research & Business Foundation Sungkyunkwan University - Inventors: Jin Hong Park; Jae Woong Choi; Je Jun Lee; Ju Hee Lee - Web page: https://patentgrep.com/patent/US12218155B2 ## CPC - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 86/60: wherein the TFTs are in active matrices - H10D 8/01: Manufacture or treatment - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs} - H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode. ## Claims ### Claim 1 A semiconductor device with multiple zero differential transconductance, the semiconductor device comprising: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on upper portions of the first insulating layer and the second insulating layer, respectively, the first semiconductor and the second semiconductor comprising electrode contact areas; a first buffer layer and a second buffer layer disposed on the electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on the upper portions of the first insulating layer and the second insulating layer where the first semiconductor and the second semiconductor are not formed, and on surfaces of the first buffer layer and the second buffer layer, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode, wherein the anode electrode connects to the first buffer layer and the second buffer layer, and the cathode electrode connects to the first buffer layer and the second buffer layer, and wherein the semiconductor device further comprises a plurality of drain current saturation regions in which the drain current is constant with respect to a change of gate voltage such that the semiconductor device has a plurality of stable logic states. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a dielectric constant of the first insulating layer and the second insulating layer are different from each other. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein a geometric structure of the first insulating layer and the second insulating layer are different from each other. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein a band structure of the first semiconductor and the second semiconductor are different from each other. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein a doping process of the first semiconductor and the second semiconductor are different from each other. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first buffer layer and the second buffer layer are formed by modifying the electrode contact areas of the first semiconductor and the second semiconductor, respectively. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the first buffer layer and the second buffer layer are disposed on the electrode contact areas of the first semiconductor and the second semiconductor using a different material from the first semiconductor and the second semiconductor, respectively. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising: a third insulating layer disposed between the first insulating layer and the conductive substrate; and a fourth insulating layer disposed between the second insulating layer and the conductive substrate. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the third insulating layer comprises a band structure to block a carrier drifting between the first insulating layer and the conductive substrate, and wherein the fourth insulating layer comprises a band structure to block a carrier drifting between the second insulating layer and the conductive substrate. ### Claim 10 A method of manufacturing a semiconductor device with multiple zero differential transconductance, the method comprising: forming a first insulating layer and a second insulating layer on a conductive substrate; forming a first semiconductor and a second semiconductor in upper portions of the first insulating layer and the second insulating layer, respectively, the first semiconductor and the second semiconductor comprising electrode contact areas; forming a first buffer layer and a second buffer layer in the electrode contact areas of the first semiconductor and the second semiconductor, respectively; and forming an anode electrode and a cathode electrode on portions of the first insulating layer and the second insulating layer where the first semiconductor and the second semiconductor are not formed, and on surfaces of the first buffer layer and the second buffer layer, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode, wherein the anode electrode connects to the first buffer layer and the second buffer layer, and the cathode electrode connects to the first buffer layer and the second buffer layer, and wherein the semiconductor device further comprises a plurality of drain current saturation regions in which the drain current is constant with respect to a change of gate voltage such that the semiconductor device has a plurality of stable logic states. ### Claim 11 (depends on 10) The method of claim 10, wherein a dielectric constant of the first insulating layer and the second insulating layer are different from each other. ### Claim 12 (depends on 10) The method of claim 10, wherein a geometric structure of the first insulating layer and the second insulating layer are different from each other. ### Claim 13 (depends on 10) The method of claim 10, wherein a band structure of the first semiconductor and the second semiconductor are different from each other. ### Claim 14 (depends on 10) The method of claim 10, wherein a doping process of the first semiconductor and the second semiconductor are different from each other. ### Claim 15 (depends on 10) The method of claim 10, wherein the first buffer layer and the second buffer layer are formed by modifying the electrode contact areas of the first semiconductor and the second semiconductor, respectively. ### Claim 16 (depends on 10) The method of claim 10, wherein the first buffer layer and the second buffer layer are formed on the electrode contact areas of the first semiconductor and the second semiconductor using a different material from the first semiconductor and the second semiconductor, respectively. ### Claim 17 (depends on 10) The method of claim 10, further comprising: forming a third insulating layer between the first insulating layer and the conductive substrate before forming the first insulating layer; and forming a fourth insulating layer between the second insulating layer and the conductive substrate before forming the second insulating layer. ### Claim 18 (depends on 17) The method of claim 17, wherein the third insulating layer comprises a band structure to block a carrier drifting between the first insulating layer and the conductive substrate, and wherein the fourth insulating layer comprises a band structure to block a carrier drifting between the second insulating layer and the conductive substrate.