# US 12,218,145 B2 · Display panel and display device

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- Number: US 12,218,145 B2
- Document ID: US12218145B2
- Status: Granted
- Kind: B2
- Application number: 18/384,565
- Filed: 2023-10-27
- Published: 2024-02-15
- Granted: 2025-02-04
- Earliest claimed: 2020-12-30
- Assignees: Xiamen Tianma Micro-Electronics Co., Ltd.
- Applicants: Xiamen Tianma Micro-Electronics Co., Ltd.
- Inventors: Qingjun Lai; Yihua Zhu; Yong Yuan; Ping An; Zhaokeng Cao
- Web page: https://patentgrep.com/patent/US12218145B2

## CPC

- G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
- H10D 86/60: wherein the TFTs are in active matrices
- G09G 3/3225: using an active matrix
- H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- G09G 2300/0404: Matrix technologies
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0465: Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
- G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10K 59/1213: {the pixel elements being TFTs}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. A length of a channel region of the second transistor is L2. Along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2.

## Claims

### Claim 1

A display panel, comprising:
a base substrate;
a first transistor and a second transistor; wherein:
the first transistor and the second transistor are formed on the base substrate; the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes an oxide semiconductor;
a length of a channel region of the first transistor is L1; along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1; and a first area S1=L1×D1; and
a length of a channel region of the second transistor is L2; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2; and a second area S2-L2×D2, wherein S1<S2; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the second transistor is included in the pixel circuit, and the first transistor is included in the pixel circuit, the first transistor is a drive transistor of the pixel circuit, and the second transistor is a switch transistor of the pixel circuit.

### Claim 2 (depends on 1)

The display panel according to claim 1, wherein:
D1/D2<L1/L2.

### Claim 3 (depends on 1)

The display panel according to claim 1, wherein:
the second transistor further includes a fourth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fourth gate electrode and the second active layer is D4, and D2<D4;
a channel region of the second transistor defined by the second gate electrode is a second channel region, and a length of the second channel region is L2;
a channel region of the second transistor defined by the fourth gate electrode is a fourth channel region, and a length of the fourth channel region is L4, and a fourth area S4=L4×D4; and
S2<S4, and/or (S4+S1)>2S2.

### Claim 4 (depends on 3)

The display panel according to claim 3, wherein:
the first transistor further includes a third gate electrode; and along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, wherein D1<D3;
a channel region of the first transistor defined by the first gate electrode is a first channel region, and a length of the first channel region is L1;
a channel region of the first transistor defined by the third gate electrode is a third channel region, and a length of the third channel region is L3, wherein a third area S3=L3×D3, and S1<S3.

### Claim 5 (depends on 4)

The display panel according to claim 4, wherein:
(S3−S1)<(S4−S2).

### Claim 6 (depends on 1)

The display panel according to claim 1, wherein:
the pixel circuit includes a third transistor; and the third transistor includes a fifth gate electrode, a third active layer, a third source electrode, and a third drain electrode; and the third active layer includes an oxide semiconductor; and
along the direction perpendicular to the base substrate, a distance between the fifth gate electrode and the third active layer is D5; a channel region of the third transistor defined by the fifth gate electrode is a fifth channel region; a length of the fifth channel region is L5; and a fifth area S5=L5×D5, wherein S1<S5.

### Claim 7 (depends on 6)

The display panel according to claim 6, wherein:
the third transistor further includes a sixth gate electrode; and along the direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6;
a channel region of the third transistor defined by the sixth gate electrode is a sixth channel region, a length of the sixth channel region is L6, and a sixth area S6=L6×D6; and
D5<D6, and/or S5<S6.

### Claim 8 (depends on 7)

The display panel according to claim 7, wherein:
the third transistor is a switch transistor of the pixel circuit, wherein S2>S5, and/or S6<S4, and/or (S4−S2)>(S6−S5); and/or
the third transistor is a drive transistor of the pixel circuit, wherein S2<S5, and/or S6>S4, and/or (S4−S2)<(S6−S5).

### Claim 9

A display panel, comprising:
a base substrate;
a first transistor and a second transistor; wherein:
the first transistor and the second transistor are formed on the base substrate; the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes an oxide semiconductor;
a length of a channel region of the first transistor is L1; along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1; and a first area S1=L1×D1; and
a length of a channel region of the second transistor is L2; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2; and a second area S2=L2×D2, wherein S1<S2; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the second transistor is included in the drive circuit, and the first transistor is included in the pixel circuit, the first transistor is a drive transistor of the pixel circuit, and the second transistor is a switch transistor of the pixel circuit.

### Claim 10 (depends on 9)

The display panel according to claim 9, wherein:
a width of the channel region of the first transistor is W1, a width of the channel region of the second transistor is W2, a first volume V1=S1×W1, and a second volume V2−S2×W2, wherein V1>V2.

### Claim 11 (depends on 9)

The display panel according to claim 9, wherein:
D1/D2<L1/L2.

### Claim 12 (depends on 9)

The display panel according to claim 9, wherein:
the second transistor further includes a fourth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fourth gate electrode and the second active layer is D4, wherein D2<D4;
a channel region of the second transistor defined by the second gate electrode is a second channel region, and a length of the second channel region is L2;
a channel region of the second transistor defined by the fourth gate electrode is a fourth channel region, and a length of the fourth channel region is L4, wherein a fourth area S4−L4×D4; and
S2<S4, and/or (S4+S1)>2S2.

### Claim 13 (depends on 12)

The display panel according to claim 12, wherein:
the first transistor further includes a third gate electrode; and along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, wherein D1<D3;
a channel region of the first transistor defined by the first gate electrode is a first channel region, and a length of the first channel region is L1;
a channel region of the first transistor defined by the third gate electrode is a third channel region, and a length of the third channel region is L3, wherein a third area S3=L3×D3, and S1<S3.

### Claim 14 (depends on 13)

The display panel according to claim 13, wherein:
(S3−S1)<(S4−S2).

### Claim 15 (depends on 9)

The display panel according to claim 9, wherein:
the pixel circuit includes a third transistor; and the third transistor includes a fifth gate electrode, a third active layer, a third source electrode, and a third drain electrode; and the third active layer includes an oxide semiconductor; and
along the direction perpendicular to the base substrate, a distance between the fifth gate electrode and the third active layer is D5; a channel region of the third transistor defined by the fifth gate electrode is a fifth channel region; a length of the fifth channel region is L5; and a fifth area S5=L5×D5, wherein S1<S5.

### Claim 16 (depends on 15)

The display panel according to claim 15, wherein:
the third transistor further includes a sixth gate electrode; and along the direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6, wherein D5<D6;
a channel region of the third transistor defined by the sixth gate electrode is a sixth channel region, a length of the sixth channel region is L6, and a sixth area S6=L6×D6, wherein S5<S6.

### Claim 17 (depends on 16)

The display panel according to claim 16, wherein:
the third transistor is a switch transistor of the pixel circuit, wherein S2>S5, and/or S6<S4, and/or (S4−S2)>(S6−S5); and/or
the third transistor is a drive transistor of the pixel circuit, wherein S2<S5, and/or S6>S4, and/or (S4−S2)<(S6−S5).

### Claim 18

A display device, comprising a display panel, the display panel comprising:
a base substrate;
a first transistor and a second transistor; wherein:
the first transistor and the second transistor are formed on the base substrate; the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes an oxide semiconductor;
a length of a channel region of the first transistor is L1; along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1; and a first area S1=L1×D1; and
a length of a channel region of the second transistor is L2; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2; and a second area S2=L2×D2, wherein S1<S2; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the second transistor is included in the pixel circuit, and the first transistor is included in the pixel circuit, the first transistor is a drive transistor of the pixel circuit, and the second transistor is a switch transistor of the pixel circuit.

### Claim 19 (depends on 9)

A display device, comprising the display panel according to claim 9.