# US 12,218,139 B2 · Semiconductor device with metal structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,218,139 B2 - Document ID: US12218139B2 - Status: Granted - Kind: B2 - Application number: 17/566,082 - Filed: 2021-12-30 - Published: 2022-10-13 - Granted: 2025-02-04 - Earliest claimed: 2021-04-09 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Jhon Jhy Liaw - Web page: https://patentgrep.com/patent/US12218139B2 ## CPC - H10D 84/907: {CMOS gate arrays} - H10D 89/10: Integrated device layouts - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10B 10/125: {the MOSFET being a thin film transistor [TFT]} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/853: {comprising FinFETs} - H10D 84/987: {Three levels of metal} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction. ## Claims ### Claim 1 A semiconductor device, comprising: a plurality of gate structures, wherein a first gate structure of the plurality of gate structures is arranged to be a first gate terminal of a first transistor, and wherein a second gate structure of the plurality of gate structures is arranged to be a second gate terminal of a second transistor; a plurality of first metal layer structures formed above the plurality of gate structures, wherein each of the plurality of first metal layer structures and one of the plurality of gate structures are crisscrossed from a top view, and wherein each of the plurality of first metal layer structures have a first thickness T1; a plurality of second metal layer structures formed above the plurality of first metal layer structures, wherein each of the plurality of second metal layer structures and one of the plurality of first metal layer structures are crisscrossed from the top view, and wherein each of the plurality of second metal layer structures have a second thickness T2; and a plurality of third metal layer structures formed above the plurality of second metal layer structures, wherein each of the plurality of third metal layer structures and one of the plurality of second metal layer structures are crisscrossed from the top view, wherein each of the plurality of third metal layer structures have a third thickness T3, wherein the second thickness T2 is greater than both the first thickness T1 and the third thickness T3; and a drain contact directly contacting both a drain feature of the first transistor and a drain feature of the second transistor together, wherein the drain contact is longer than each of a first source contact of the first transistor and a second source contact of the second transistor. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the plurality of first metal layer structures have a first minimum pitch P1, wherein the plurality of second metal layer structures have a second minimum pitch P2, wherein the plurality of third metal layer structures have a third minimum pitch P3, wherein the second minimum pitch P2 is greater than both the first minimum pitch P1 and the third minimum pitch P3. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the third minimum pitch P3 is greater than the first minimum pitch P1. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein the plurality of gate structures have a minimum pitch Pg, and wherein the second minimum pitch P2 is substantially same as the minimum pitch Pg. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein a first ratio of the second minimum pitch P2 over the third minimum pitch P3 is in a range of 1.1-2.0. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the first ratio is 1.2. ### Claim 7 (depends on 2) The semiconductor device of claim 2, wherein a second ratio of the third minimum pitch P3 over the first minimum pitch P1 is in a range of 1.1-2.0. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein a first thickness ratio of T2/T3 is equal to or greater than 1.2. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein a second thickness ratio of T2/T1 is equal to or greater than 1.2. ### Claim 10 A semiconductor device comprising: a substrate having a first region and a second region, the first active region being associated with a first transistor and the second active region being associated with a second transistor; a first active region disposed in the first region of the substrate; a second active region disposed in the second region of the substrate; a first gate stack disposed over the first active region and a second gate stack disposed over the second active region, wherein the first gate stack and the second gate stack have elongated shapes oriented in a first direction; a first metal layer disposed over the first gate stack and the second gate stack, wherein the first metal layer comprises a plurality of first metal layer structures oriented in a second direction, the second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, wherein the second metal layer comprises a plurality of second metal layer structures oriented in the first direction; and a third metal layer disposed over the second metal layer, wherein the third metal layer comprises a plurality of third metal layer structures oriented in the second direction, wherein: the plurality of first metal layer structures have a first minimum pitch P1, the plurality of second metal layer structures have a second minimum pitch P2, the plurality of third metal layer structures have a third minimum pitch P3, and the second minimum pitch P2 is greater than both the first minimum pitch P1 and the third minimum pitch P3; a drain contact directly contacting both a drain feature of the first transistor and a drain feature of the second transistor together, wherein the drain contact is longer than each of a first source contact of the first transistor and a second source contact of the second transistor. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the first gate stack and the second gate stack have a minimum pitch Pg, and wherein the second minimum pitch P2 is same as the minimum pitch Pg. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein a first ratio of the second minimum pitch P2 over the third minimum pitch P3 is in a range of 1.1-2.0, and wherein a second ratio of the third minimum pitch P3 over the first minimum pitch P1 is in a range of 1.1-2.0. ### Claim 13 (depends on 10) The semiconductor device of claim 10, wherein each of the plurality of first metal layer structures have a first thickness T1, wherein each of the plurality of second metal layer structures have a second thickness T2, wherein each of the plurality of third metal layer structures have a third thickness T3, and wherein the second thickness T2 is greater than both the first thickness T1 and the third thickness T3. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein a first thickness ratio of T2/T3 is equal to or greater than 1.2, and wherein a second thickness ratio of T2/T1 is equal to or greater than 1.2. ### Claim 15 (depends on 13) The semiconductor device of claim 13, further comprising a first dielectric gate stack disposed between the first region and the second region of the substrate, the first dielectric gate stack electrically isolating the first region from the second region of the substrate. ### Claim 16 A semiconductor device comprising: a substrate; a first active region and a second active region over the substrate and oriented lengthwise generally along a first direction; a gate electrode over the substrate and oriented lengthwise generally along a second direction perpendicular to the first direction, wherein the gate electrode engages the first active region to form a first transistor and engages the second active region to form a second transistor; a first source contact oriented lengthwise generally along the second direction, the first source contact directly contacting a source feature of the first transistor; a second source contact oriented lengthwise generally along the second direction, the second source contact directly contacting a source feature of the second transistor; and a drain contact oriented lengthwise generally along the second direction, the drain contact directly contacting both a drain feature of the first transistor and a drain feature of the second transistor together. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the drain contact is longer than each of the first source contact and the second source contact. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein the first transistor is a p-channel Metal Oxide Semiconductor (PMOS) transistor and the second transistor is a n-channel Metal Oxide Semiconductor (NMOS) transistor. ### Claim 19 (depends on 16) The semiconductor device of claim 16, wherein the first transistor and the second transistor are connected to form an invertor. ### Claim 20 (depends on 16) The semiconductor device of claim 16, further comprising: a first metal layer disposed over the first source contact, the second source contact, and the drain contact, wherein the first metal layer comprises a plurality of first metal layer structures oriented in the first direction, the second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, wherein the second metal layer comprises a plurality of second metal layer structures oriented in the second direction; and a third metal layer disposed over the second metal layer, wherein the third metal layer comprises a plurality of third metal layer structures oriented in the first direction.