# US 12,218,138 B2 · Air gap formation between gate spacer and epitaxy structure

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- Number: US 12,218,138 B2
- Document ID: US12218138B2
- Status: Granted
- Kind: B2
- Application number: 18/510,370
- Filed: 2023-11-15
- Published: 2024-03-14
- Granted: 2025-02-04
- Earliest claimed: 2018-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Bo-Yu Lai; Kai-Hsuan Lee; Wei-Yang Lee; Feng-Cheng Yang; Yen-Ming Chen
- Web page: https://patentgrep.com/patent/US12218138B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

## Claims

### Claim 1

A semiconductor device, comprising:
source/drain regions over a substrate;
a gate structure laterally between the source/drain regions;
a first gate spacer on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region; and
a dielectric material between the first one of the source/drain regions and the void region, the dielectric material having a gradient ratio of a first chemical element to a second chemical element.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first chemical element is silicon.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second chemical element is nitrogen.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first gate spacer comprises a vertical portion on the first sidewall of the gate structure, and a horizontal portion directly below the dielectric material.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gradient ratio of the first chemical element to the second chemical element increases as a distance from the horizontal portion of the first gate spacer increases.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the dielectric material has a density increasing as a distance from the horizontal portion of the first gate spacer increases.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second gate spacer extending from the first gate spacer to over the first one of the source/drain regions, the second gate spacer defining a top boundary of the void region.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the dielectric material is spaced apart from the second gate spacer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first one of the source/drain regions has an inner sidewall facing the void region, and an interface formed by the inner sidewall and the dielectric material is more linear than an upper portion of the inner sidewall that is spaced apart from the dielectric material.

### Claim 10

A semiconductor device, comprising:
a gate structure extending across a semiconductor fin;
source/drain epitaxial regions on the semiconductor fin and spaced apart from the gate structure at least by air-containing regions; and
a dielectric structure between a first one of the source/drain epitaxial regions and a first one of the air-containing regions, the dielectric structure having a gradient density.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the gradient density of the dielectric structure increases as a distance from the semiconductor fin increases.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the dielectric structure is silicon nitride.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the dielectric structure has a gradient silicon-to-nitrogen atomic ratio.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the gradient silicon-to-nitrogen atomic ratio increases as a distance from the semiconductor fin increases.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising:
a first gate spacer on a first sidewall of the gate structure, the first gate spacer having an L-shaped cross-sectional pattern bordering the first one of the first air-containing regions; and
a second gate spacer on a second sidewall of the gate structure, the second gate spacer having an L-shaped cross-sectional pattern bordering a second one of the first air-containing regions.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising:
a third gate spacer alongside the first gate spacer and over the first one of the source/drain epitaxial regions, the third gate spacer defining a top border of the first one of the first air-containing regions; and
a fourth gate spacer alongside the second gate spacer and over a second one of the source/drain epitaxial regions, the fourth gate spacer defining a top border of the second one of the first air-containing regions.

### Claim 17

A semiconductor device, comprising:
an n-type transistor comprising a first gate structure and n-type source/drain regions on opposite sides of the first gate structure, the first gate structure being spaced apart from the n-type source/drain regions at least by first air-containing regions; and
a p-type transistor comprising a second gate structure and p-type source/drain regions on opposite sides of the second gate structure, the second gate structure being spaced apart from the p-type source/drain regions at least by second air-containing regions,
wherein the n-type source/drain regions have inner surfaces facing the first air-containing regions, and the p-type source/drain regions have inner surfaces facing the second air-containing regions, and the inner surfaces of the n-type source/drain regions are rougher than the inner surfaces of the p-type source/drain regions.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein each of the inner surfaces of the n-type source/drain regions has a residue-containing region and a residue-free region over the residue-containing region, and the residue-free regions are rougher than the residue-containing regions.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein dielectric residues on the residue-containing regions of the inner surfaces of the n-type source/drain regions have a gradient ratio of silicon to nitrogen.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein dielectric residues on the residue-containing regions of the inner surfaces of the n-type source/drain regions have a gradient density.