# US 12,218,137 B2 · Structure and method for gate-all-around metal-oxide-semiconductor devices with improved channel configurations

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,218,137 B2
- Document ID: US12218137B2
- Status: Granted
- Kind: B2
- Application number: 18/447,407
- Filed: 2023-08-10
- Published: 2023-12-07
- Granted: 2025-02-04
- Earliest claimed: 2019-10-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US12218137B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure provides an integrated circuit device that comprises a semiconductor substrate having a top surface; a first and a second source/drain features over the semiconductor substrate; a first semiconductor layer extending in parallel with the top surface and connecting the first and the second source/drain features, the first semiconductor layer having a center portion and two end portions, each of the two end portions connecting the center portion and one of the first and second source/drain features; a first spacer over the two end portions of the first semiconductor layer; a second spacer vertically between the two end portions of the first semiconductor layer and the top surface; and a gate electrode wrapping around and engaging the center portion of the first semiconductor layer. The center portion has a thickness smaller than the two end portions.

## Claims

### Claim 1

A device structure, comprising:
a base fin arising from a substrate;
a first source/drain feature and a second source/drain feature disposed over the base fin;
a plurality of nanostructures extending between and in contact with the first source/drain feature and the second source/drain feature along a direction;
a metal gate structure wrapping around each of the plurality of nanostructures; and
a first dielectric gate structure and a second dielectric gate structure disposed over the base fin,
wherein the first source/drain feature, the metal gate structure and the second source/drain feature are disposed between the first dielectric gate structure and the second dielectric gate structure along the direction,
wherein, along the direction, the first dielectric gate structure is spaced apart from the first source/drain feature by a stack of semiconductor layers interleaved by a stack of inner spacer features.

### Claim 2 (depends on 1)

The device structure of claim 1, wherein the base fin comprises a doped well region.

### Claim 3 (depends on 1)

The device structure of claim 1, wherein the first dielectric gate structure and the second dielectric gate structure comprise silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, carbon-doped oxide, nitrogen-doped oxide, carbon-doped and nitrogen-doped oxide, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum-doped oxide, or combinations thereof.

### Claim 4 (depends on 1)

The device structure of claim 1, wherein the metal gate structure comprise titanium nitride, tantalum nitride, titanium aluminide, titanium aluminum nitride, tantalum aluminide, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, copper, cobalt, nickel, platinum, or combinations thereof.

### Claim 5 (depends on 1)

The device structure of claim 1, further comprising:
a silicide feature disposed on the first source/drain feature; and
a source/drain contact over the silicide feature.

### Claim 6 (depends on 5)

The device structure of claim 5, wherein, along the direction, the first dielectric gate structure is spaced apart from the source/drain contact by a gate spacer.

### Claim 7 (depends on 1)

The device structure of claim 1, wherein the stack of semiconductor layers comprises silicon or silicon germanium.

### Claim 8 (depends on 1)

The device structure of claim 1, wherein each of the first dielectric gate structure and the second dielectric gate structure partially extends into the base fin such that a bottom surface of the first dielectric gate structure or the second dielectric gate structure is lower than a bottom surface of the metal gate structure.

### Claim 9 (depends on 1)

The device structure of claim 1, wherein a sidewall of the first dielectric gate structure is in contact with the stack of semiconductor layers and the stack of inner spacer features.

### Claim 10

A semiconductor structure, comprising:
a base fin arising from a substrate and extending lengthwise along a direction;
a plurality of nanostructures disposed over the base fin;
a metal gate structure wrapping around each of the plurality of nanostructures;
a dielectric gate structure disposed over and partially extending into the base fin; and
a source/drain feature disposed between the metal gate structure and the dielectric gate structure along the direction,
wherein the dielectric gate structure is spaced apart from the source/drain feature by a stack of semiconductor layers interleaved by a stack of inner spacer features.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the plurality of the nanostructures and the stack of semiconductor layers share the same composition.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, wherein the plurality of the nanostructures and the stack of semiconductor layers comprise silicon or silicon germanium.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, further comprising:
a silicide feature disposed on the source/drain feature; and
a source/drain contact over the silicide feature.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein, along the direction, the dielectric gate structure is spaced apart from the source/drain contact by a gate spacer.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, further comprising:
a gate top dielectric layer disposed over the dielectric gate structure and the gate spacer,
wherein the gate top dielectric layer is in direct contact with the source/drain contact.

### Claim 16

A semiconductor structure, comprising:
a base fin arising from a substrate and extending lengthwise along a first direction;
a plurality of nanostructures disposed over the base fin;
a metal gate structure wrapping around each of the plurality of nanostructures and extending lengthwise along a second direction perpendicular to the first direction;
a pair of gate end dielectric layers sandwiching the metal gate structure along the second direction;
a dielectric gate structure disposed over the base fin; and
a source/drain feature disposed between the metal gate structure and the dielectric gate structure along the first direction; and
a source/drain contact over the source/drain feature,
wherein, along the first direction, the dielectric gate structure is spaced apart from the source/drain contact by a gate spacer,
wherein, along the first direction, the dielectric gate structure is spaced apart from the source/drain feature by a stack of semiconductor layers interleaved by a stack of inner spacer features.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein a dielectric constant of the pair of gate end dielectric layers is greater than a dielectric constant of the gate spacer or a dielectric constant of the stack of inner spacer features.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein the dielectric gate structure partially extends into the base fin.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, further comprising:
an isolation feature over the substrate,
wherein the base fin is disposed in the isolation feature,
wherein the dielectric gate structure partially extends into the isolation feature.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, further comprising:
a silicide feature disposed between the source/drain feature and the source/drain contact,
wherein the silicide feature is spaced apart from the dielectric gate structure by the gate spacer along the first direction.