# US 12,218,133 B2 · Three-dimensional semiconductor device and method of fabricating the same

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- Number: US 12,218,133 B2
- Document ID: US12218133B2
- Status: Granted
- Kind: B2
- Application number: 17/805,261
- Filed: 2022-06-03
- Published: 2023-05-04
- Granted: 2025-02-04
- Earliest claimed: 2021-10-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sungil Park; Jae Hyun Park; Daewon Ha; Kyuman Hwang
- Web page: https://patentgrep.com/patent/US12218133B2

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

## Claims

### Claim 1

A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction;
a second active region on the first active region, the second active region including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction;
a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns; and
a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns,
wherein the first gate electrode includes:
a first lower gate electrode on the first lower channel pattern; and
a first upper gate electrode on the first upper channel pattern,
wherein the first lower gate electrode and the first upper gate electrode are connected to each other,
wherein the second gate electrode includes:
a second lower gate electrode on the second lower channel pattern;
a second upper gate electrode on the second upper channel pattern; and
an isolation pattern between the second lower gate electrode and the second upper gate electrode, and
wherein the second lower gate electrode and the second upper gate electrode are separated from each other by the isolation pattern.

### Claim 2 (depends on 1)

The device of claim 1, wherein
the first lower channel pattern and the first upper channel pattern vertically overlap each other, and
the second lower channel pattern and the second upper channel pattern vertically overlap each other.

### Claim 3 (depends on 1)

The device of claim 1, further comprising:
a first dummy channel pattern between the first lower channel pattern and the first upper channel pattern; and
a second dummy channel pattern between the second lower channel pattern and the second upper channel pattern.

### Claim 4 (depends on 3)

The device of claim 3, wherein each of the first and second dummy channel patterns includes a silicon oxide layer or a silicon nitride layer.

### Claim 5 (depends on 1)

The device of claim 1, wherein
each of the first and second lower channel patterns includes a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern,
each of the first and second lower gate electrodes surrounds the first and second semiconductor patterns,
each of the first and second upper channel patterns includes a third semiconductor pattern and a fourth semiconductor pattern on the third semiconductor pattern, and
each of the first and second upper gate electrodes surrounds the third and fourth semiconductor patterns.

### Claim 6 (depends on 1)

The device of claim 1, wherein each of the first and second lower gate electrodes includes:
a first metal pattern that includes a first work-function metal;
a second metal pattern on the first metal pattern, the second metal pattern including a second work-function metal; and
a third metal pattern on the second metal pattern, the third metal pattern including a low-resistance metal,
wherein a thickness of the third metal pattern included in the first lower gate electrode is greater than a thickness of the third metal pattern included in the second lower gate electrode.

### Claim 7 (depends on 6)

The device of claim 6, wherein the thickness of the third metal pattern included in the first lower gate electrode is substantially the same as a sum of the thickness of the third metal pattern included in the second lower gate electrode and a thickness of the isolation pattern.

### Claim 8 (depends on 1)

The device of claim 1, further comprising:
a lower gate dielectric layer between the first lower channel pattern and the first lower gate electrode; and
an upper gate dielectric layer between the first upper channel pattern and the first upper gate electrode,
wherein the lower gate dielectric layer contains a dipole element, and
wherein a concentration of the dipole element in the lower gate dielectric layer is greater than a concentration of the dipole element in the upper gate dielectric layer.

### Claim 9 (depends on 1)

The device of claim 1, further comprising:
an upper gate contact coupled to the second upper gate electrode;
a lower gate contact coupled to the second lower gate electrode;
a first wiring line electrically connected to the upper gate contact; and
a second wiring line electrically connected to the lower gate contact.

### Claim 10 (depends on 9)

The device of claim 9, further comprising a contact spacer on a sidewall of the lower gate contact,
wherein the lower gate contact penetrates and is insulated from the second upper gate electrode by the contact spacer.

### Claim 11

A three-dimensional semiconductor device, comprising:
a first active region on a substrate and a second active region on the first active region;
a first gate electrode and a second gate electrode on the first active region and the second active region,
wherein the first gate electrode includes
a first lower gate electrode on the first active region,
a first upper gate electrode on the second active region, and
a first isolation pattern between the first lower gate electrode and the first upper gate electrode, and
wherein the second gate electrode includes
a second lower gate electrode on the first active region,
a second upper gate electrode on the second active region, and
a second isolation pattern between the second lower gate electrode and the second upper gate electrode;
a first upper gate contact coupled to the first upper gate electrode;
a first lower gate contact coupled to the first lower gate electrode;
a second upper gate contact coupled to the second upper gate electrode;
a second lower gate contact coupled to the second lower gate electrode;
a first wiring line electrically connected to the first upper gate contact and the second lower gate contact; and
a second wiring line electrically connected to the first lower gate contact and the second upper gate contact.

### Claim 12 (depends on 11)

The device of claim 11, wherein
the first wiring line is configured to allow a first signal to be applied therethrough to the first upper gate electrode and the second lower gate electrode,
the second wiring line is configured to allow a second signal to be applied therethrough to the second upper gate electrode and the first lower gate electrode, and
the second signal is an inverse signal to the first signal.

### Claim 13 (depends on 11)

The device of claim 11, wherein
the first lower gate electrode and the first upper gate electrode vertically overlap each other,
the first lower gate electrode and the first upper gate electrode are separated from each other by the first isolation pattern,
the second lower gate electrode and the second upper gate electrode vertically overlap each other, and
the second lower gate electrode and the second upper gate electrode are separated from each other by the second isolation pattern.

### Claim 14 (depends on 11)

The device of claim 11, wherein
each of the first and second lower gate electrodes surrounds a plurality of semiconductor patterns of the first active region, and
each of the first and second upper gate electrodes surrounds a plurality of semiconductor patterns of the second active region.

### Claim 15 (depends on 11)

The device of claim 11, further comprising a dummy channel pattern between the first active region and the second active region,
wherein a top surface of each of the first and second isolation patterns is at a level between levels of top and bottom surfaces of the dummy channel pattern.

### Claim 16

A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern;
a second active region on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern;
a dummy channel pattern between the lower channel pattern and the upper channel pattern; and
a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern,
wherein the gate electrode includes:
a lower gate electrode on the lower channel pattern;
an upper gate electrode on the upper channel pattern; and
an isolation pattern between the lower gate electrode and the upper gate electrode.

### Claim 17 (depends on 16)

The device of claim 16, wherein the lower gate electrode and the upper gate electrode are separated from each other by the isolation pattern.

### Claim 18 (depends on 16)

The device of claim 16, wherein a top surface of the isolation pattern is at a level between levels of top and bottom surfaces of the dummy channel pattern.

### Claim 19 (depends on 16)

The device of claim 16, wherein
the lower channel pattern includes a first semiconductor pattern,
the upper channel pattern includes a second semiconductor pattern,
the dummy channel pattern includes a dielectric material, and
the first semiconductor pattern, the second semiconductor pattern, and the dummy channel pattern vertically overlap each other.

### Claim 20 (depends on 16)

The device of claim 16, further comprising:
an upper gate contact coupled to the upper gate electrode;
a lower gate contact coupled to the lower gate electrode;
a first wiring line electrically connected to the upper gate contact; and
a second wiring line electrically connected to the lower gate contact.